CD4007UBM

{
  "schema_version": 1,
  "type": "component",
  "slug": "cd4007ubm",
  "title": "CD4007UBM",
  "brief": "HGSEMI Inverters, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "cd4007ubm"
  ],
  "component": {
    "mpn": "CD4007UBM",
    "manufacturer": "HGSEMI",
    "package": "SOP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Inverters",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/4c5a8947a75a55779e0f2163e148ed15.pdf",
    "parts": {
      "symbol": "cd4007ubm.kicad_sym",
      "footprint": "cd4007ubm.kicad_mod",
      "model_3d": "cd4007ubm-etched.glb",
      "model_3d_plain": "cd4007ubm.glb",
      "model_3d_step": "cd4007ubm-etched.step",
      "model_3d_step_plain": "cd4007ubm.step",
      "lbr": "cd4007ubm.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "Q2_PD",
        "type": "passive",
        "description": "Q2 P-channel MOSFET DRAIN terminal. Also serves as the output node when Q2 is used as a complementary inverter (tied with pin 5, Q2 N-drain)."
      },
      {
        "number": "2",
        "name": "Q2_PS",
        "type": "passive",
        "description": "Q2 P-channel MOSFET SOURCE terminal. Typically tied to VDD when Q2 is used as a standard CMOS inverter/gate element."
      },
      {
        "number": "3",
        "name": "Q2_G",
        "type": "input",
        "description": "Q2 common GATE terminal (both P- and N-channel gates of the Q2 complementary pair are tied together). Used as the input of the Q2 CMOS inverter."
      },
      {
        "number": "4",
        "name": "Q2_NS",
        "type": "passive",
        "description": "Q2 N-channel MOSFET SOURCE terminal. Typically tied to VSS when Q2 is used as a standard CMOS inverter/gate element."
      },
      {
        "number": "5",
        "name": "Q2_ND",
        "type": "passive",
        "description": "Q2 N-channel MOSFET DRAIN terminal. Combines with pin 1 (Q2 P-drain) to form the Q2 inverter output node in a typical CMOS configuration."
      },
      {
        "number": "6",
        "name": "Q1_G",
        "type": "input",
        "description": "Q1 common GATE terminal (both P- and N-channel gates of the Q1 pair). Q1's P-drain and N-source are internally strapped to VDD (pin 14) and VSS (pin 7) respectively, so Q1 is pre-wired as a standalone inverter."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply / ground rail. Also the common substrate connection for all N-channel devices (Q1, Q2, Q3 N-substrates) and Q1's N-channel source."
      },
      {
        "number": "8",
        "name": "Q1_ND",
        "type": "passive",
        "description": "Q1 N-channel MOSFET DRAIN terminal. Combined with pin 13 (Q1 P-source) to expose the Q1 inverter output; when Q1 is used as a fixed inverter this is the low-side of the output."
      },
      {
        "number": "9",
        "name": "Q3_NS",
        "type": "passive",
        "description": "Q3 N-channel MOSFET SOURCE terminal. Typically tied to VSS when Q3 is used as a standard CMOS inverter/gate element."
      },
      {
        "number": "10",
        "name": "Q3_G",
        "type": "input",
        "description": "Q3 common GATE terminal (both P- and N-channel gates of the Q3 complementary pair). Used as the input of the Q3 CMOS inverter."
      },
      {
        "number": "11",
        "name": "Q3_PD",
        "type": "passive",
        "description": "Q3 P-channel MOSFET DRAIN terminal. Available for use as an output node or for building series/parallel MOSFET topologies (NOR/NAND/tree logic)."
      },
      {
        "number": "12",
        "name": "Q3_ND_PS",
        "type": "passive",
        "description": "Common node: Q3 N-channel DRAIN and Q3 P-channel SOURCE tied together internally. Serves as the Q3 inverter output when Q3 is wired as a standard CMOS inverter."
      },
      {
        "number": "13",
        "name": "Q1_PS",
        "type": "passive",
        "description": "Q1 P-channel MOSFET SOURCE terminal. In the pre-wired 'plus inverter' Q1, this pin is the P-side of the inverter output and is typically tied with pin 8 (Q1 N-drain)."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply rail (3 V to 15 V recommended, 15 V absolute max). Also the common substrate connection for all P-channel devices (Q1, Q2, Q3 P-substrates) and Q1's P-channel drain."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/4c5a8947a75a55779e0f2163e148ed15.pdf",
        "pages": 13,
        "sha256": "284450e1a0d8c60d",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "CD4007",
      "logic_family": "CD4000",
      "function_code": "4007",
      "function_class": null,
      "function_name": null,
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "cd4007ubm.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4007ubm-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "47c56a7009ab37eb40c9cc006f56e88a281602ccd6feaa6ba4c45cc761c2d0a7",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "HGSEMI",
      "Package": "SOP-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "variants": [
    {
      "mpn": "CD4007UBMM/TR",
      "kind": "packaging"
    },
    {
      "mpn": "CD4007UBME",
      "kind": "packaging"
    },
    {
      "mpn": "CD4007UBMN",
      "kind": "packaging"
    },
    {
      "mpn": "CD4007UBMMT/TR",
      "kind": "packaging"
    }
  ],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "cd4007ubm"
  ],
  "discovery_pitch": "CD4007UBM (HGSEMI) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4007ubm.kicad_sym",
    "cd4007ubm.kicad_mod",
    "cd4007ubm.glb",
    "cd4007ubm.step",
    "cd4007ubm.lbr",
    "docs/hero.png",
    "docs/cd4007ubm-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T18:36:53.002Z"
}