component
CD4007UBE
Public Made by Adomby adom
lingxingic Inverters, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
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"version": "0.1.0",
"type": "component",
"description": "lingxingic Inverters, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"logic",
"cd4007ube",
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"extractor-text"
],
"dependencies": {},
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"cd4007ube.kicad_mod",
"cd4007ube.glb",
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"cd4007ube.lbr",
"docs/hero.png",
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"viewers/symbol.html",
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"component": {
"mpn": "CD4007UBE",
"manufacturer": "lingxingic",
"package": "DIP-14",
"pin_count": 14,
"category": "Logic",
"subcategory": "Inverters",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603388942091759616",
"parts": {
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"lbr": "cd4007ube.lbr"
},
"distributor_links": {
"lcsc": "C32710663",
"digikey": "296-3501-5-ND",
"mouser": "595-CD4007UBE"
},
"distributor_check": {
"checked_at": "2026-10-15T16:41:57Z",
"source": "Component Ocean /api/assign-pns",
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"status": "found"
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"pins": [
{
"number": "1",
"name": "DP2",
"type": "passive",
"description": "Drain terminal of the P2 transistor."
},
{
"number": "2",
"name": "SP2",
"type": "passive",
"description": "Source terminal of the P2 transistor."
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{
"number": "3",
"name": "G2",
"type": "input",
"description": "Common gate terminal for P2 and N2 transistors."
},
{
"number": "4",
"name": "SN2",
"type": "passive",
"description": "Source terminal of the N2 transistor."
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{
"number": "5",
"name": "DN2",
"type": "passive",
"description": "Drain terminal of the N2 transistor."
},
{
"number": "6",
"name": "G1",
"type": "input",
"description": "Common gate terminal for P1 and N1 transistors."
},
{
"number": "7",
"name": "VSS",
"type": "power_in",
"description": "Ground reference pin; the device is referenced to VSS (normally ground)."
},
{
"number": "8",
"name": "DN1",
"type": "passive",
"description": "Drain terminal of the N1 transistor."
},
{
"number": "9",
"name": "SN3",
"type": "passive",
"description": "Source terminal of the N3 transistor."
},
{
"number": "10",
"name": "G3",
"type": "input",
"description": "Common gate terminal for P3 and N3 transistors."
},
{
"number": "11",
"name": "SP3",
"type": "passive",
"description": "Source terminal of the P3 transistor."
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{
"number": "12",
"name": "DN/P3",
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"description": "Common drain terminal of the N3 and P3 transistors."
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{
"number": "13",
"name": "DP1",
"type": "passive",
"description": "Drain terminal of the P1 transistor."
},
{
"number": "14",
"name": "VDD",
"type": "power_in",
"description": "Positive supply pin; recommended supply range is 3 V to 15 V referenced to VSS."
}
],
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"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
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"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The pin-arrangement diagram (section 2.2, page 4) is an image with no extractable text, so the pin n; Pin types for drain/source terminals (passive) and the gate/supply classification are inferred from ; Section 3.1 gives absolute maximum VCC of -0.5 V to +4.6 V, which conflicts with the recommended sup"
],
"pages_sent": 15,
"cost_usd": 0.0457,
"at": "2026-10-15T16:41:40"
},
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"pages": 15,
"sha256": "83ac607da8807051",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 14,
"described": 14,
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"refuses_to_fabricate": true
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