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CD4001UBPWR

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Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs cd4001ubpwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers cd4001ubpwr: viewers · Ray 4d ago
cd4001ubpwr-etched.fit.json cd4001ubpwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
cd4001ubpwr-etched.glb cd4001ubpwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
cd4001ubpwr-etched.step cd4001ubpwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
cd4001ubpwr.glb Publish 0.1.0 · Ray 4d ago
cd4001ubpwr.kicad_mod Publish 0.1.0 · Ray 4d ago
cd4001ubpwr.kicad_sym Publish 0.1.0 · Ray 4d ago
cd4001ubpwr.lbr Publish 0.1.0 · Ray 4d ago
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README.md Initial commit: component/cd4001ubpwr · Ray 4d ago

CD4001UBPWR

Texas Instruments · Logic Gates · TSSOP-14

CD4001UBPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Gate 1 input A (J = NOR of A and B); input range -0.5 V to VDD+0.5 V.
2 B input Gate 1 input B (J = NOR of A and B); input range -0.5 V to VDD+0.5 V.
3 J output Gate 1 output, J = NOR(A,B).
4 K output Gate 2 output, K = NOR(C,D).
5 C input Gate 2 input C (K = NOR of C and D); input range -0.5 V to VDD+0.5 V.
6 D input Gate 2 input D (K = NOR of C and D); input range -0.5 V to VDD+0.5 V.
7 VSS power_in Ground / negative supply terminal; all voltages are referenced to VSS.
8 E input Gate 3 input E (L = NOR of E and F); input range -0.5 V to VDD+0.5 V.
9 F input Gate 3 input F (L = NOR of E and F); input range -0.5 V to VDD+0.5 V.
10 L output Gate 3 output, L = NOR(E,F).
11 M output Gate 4 output, M = NOR(G,H).
12 G input Gate 4 input G (M = NOR of G and H); input range -0.5 V to VDD+0.5 V.
13 H input Gate 4 input H (M = NOR of G and H); input range -0.5 V to VDD+0.5 V.
14 VDD power_in Positive supply; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: CD4001UBPWR
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4001ubpwr-etched.step / cd4001ubpwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4001ubpwr.step / cd4001ubpwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (19 pp, sha256 8bd8a869d467b734, retrieved 2026-10-01, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF