component
CD4001UBM96
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Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# CD4001UBM96++**Texas Instruments** · Logic Gates · SOIC-14++CD4001UBM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | Input A to NOR gate 1 (output J = A+B); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C). |+| 2 | B | input | Input B to NOR gate 1 (output J = A+B); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C). |+| 3 | J | output | Output of NOR gate 1 (J = A+B); output low-level voltage max 0.05 V and output high-level voltage min 4.95 V at VDD = 5 V, dissipation per output transistor limited to 100 mW over the full package-temperature range. |+| 4 | K | output | Output of NOR gate 2 (K = C+D); output low-level voltage max 0.05 V and output high-level voltage min 4.95 V at VDD = 5 V, dissipation per output transistor limited to 100 mW over the full package-temperature range. |+| 5 | C | input | Input C to NOR gate 2 (output K = C+D); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C). |+| 6 | D | input | Input D to NOR gate 2 (output K = C+D); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C). |+| 7 | VSS | power_in | Negative supply/ground reference for all four NOR gates; DC supply-voltage range (VDD referenced to this pin) is -0.5 V to +20 V absolute maximum, 3 V to 18 V recommended operating range. |+| 8 | E | input | Input E to NOR gate 3 (output L = E+F); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C). |+| 9 | F | input | Input F to NOR gate 3 (output L = E+F); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C). |+| 10 | L | output | Output of NOR gate 3 (L = E+F); output low-level voltage max 0.05 V and output high-level voltage min 4.95 V at VDD = 5 V, dissipation per output transistor limited to 100 mW over the full package-temperature range. |+| 11 | M | output | Output of NOR gate 4 (M = G+H); output low-level voltage max 0.05 V and output high-level voltage min 4.95 V at VDD = 5 V, dissipation per output transistor limited to 100 mW over the full package-temperature range. |+| 12 | G | input | Input G to NOR gate 4 (output M = G+H); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C). |+| 13 | H | input | Input H to NOR gate 4 (output M = G+H); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C). |+| 14 | VDD | power_in | Positive supply pin for all four NOR gates; recommended operating range 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `CD4001UBM96`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `cd4001ubm96-etched.step` / `cd4001ubm96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4001ubm96.step` / `cd4001ubm96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd4001ub) (19 pp, sha256 `8bd8a869d467b734`, retrieved 2026-09-23, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-5` (text+vision), consensus `claude-opus-4-8` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4001ubm96-datasheet.pdf)
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accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."+ },+ {+ "number": "2",+ "name": "B",+ "type": "input",+ "description": "Input B to NOR gate 1 (output J = A+B); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."+ },+ {+ "number": "3",+ "name": "J",+ "type": "output",+ "description": "Output of NOR gate 1 (J = A+B); output low-level voltage max 0.05 V and output high-level voltage min 4.95 V at VDD = 5 V, dissipation per output transistor limited to 100 mW over the full package-temperature range."+ },+ {+ "number": "4",+ "name": "K",+ "type": "output",+ "description": "Output of NOR gate 2 (K = C+D); output low-level voltage max 0.05 V and output high-level voltage min 4.95 V at VDD = 5 V, dissipation per output transistor limited to 100 mW over the full package-temperature range."+ },+ {+ "number": "5",+ "name": "C",+ "type": "input",+ "description": "Input C to NOR gate 2 (output K = C+D); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."+ },+ {+ "number": "6",+ "name": "D",+ "type": "input",+ "description": "Input D to NOR gate 2 (output K = C+D); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Negative supply/ground reference for all four NOR gates; DC supply-voltage range (VDD referenced to this pin) is -0.5 V to +20 V absolute maximum, 3 V to 18 V recommended operating range."+ },+ {+ "number": "8",+ "name": "E",+ "type": "input",+ "description": "Input E to NOR gate 3 (output L = E+F); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."+ },+ {+ "number": "9",+ "name": "F",+ "type": "input",+ "description": "Input F to NOR gate 3 (output L = E+F); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."+ },+ {+ "number": "10",+ "name": "L",+ "type": "output",+ "description": "Output of NOR gate 3 (L = E+F); output low-level voltage max 0.05 V and output high-level voltage min 4.95 V at VDD = 5 V, dissipation per output transistor limited to 100 mW over the full package-temperature range."+ },+ {+ "number": "11",+ "name": "M",+ "type": "output",+ "description": "Output of NOR gate 4 (M = G+H); output low-level voltage max 0.05 V and output high-level voltage min 4.95 V at VDD = 5 V, dissipation per output transistor limited to 100 mW over the full package-temperature range."+ },+ {+ "number": "12",+ "name": "G",+ "type": "input",+ "description": "Input G to NOR gate 4 (output M = G+H); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."+ },+ {+ "number": "13",+ "name": "H",+ "type": "input",+ "description": "Input H to NOR gate 4 (output M = G+H); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply pin for all four NOR gates; recommended operating range 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-4-8",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin-to-number assignment was read from the functional-diagram and schematic-diagram figures (page 1 ",+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 19,+ "cost_usd": 0.6044,+ "at": "2026-09-23T20:08:47"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd4001ub",+ "pages": 19,+ "sha256": "8bd8a869d467b734",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}