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CD4001BMT

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HGSEMI Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4001BMT

HGSEMI · Logic Gates · TSSOP-14

CD4001BMT from HGSEMI, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input A of NOR gate 1; the datasheet states that unused inputs must be tied to VDD, VSS or another input, and input voltage must stay between 0 V and VDD.
2 1B input Data input B of NOR gate 1; unused inputs must be tied to VDD, VSS or another input, and input voltage must stay between 0 V and VDD.
3 1Y output Output of NOR gate 1, which is fully buffered for high noise immunity and pattern insensitivity.
4 2Y output Output of NOR gate 2, which is fully buffered for high noise immunity and pattern insensitivity.
5 2A input Data input A of NOR gate 2; unused inputs must be tied to VDD, VSS or another input, and input voltage must stay between 0 V and VDD.
6 2B input Data input B of NOR gate 2; unused inputs must be tied to VDD, VSS or another input, and input voltage must stay between 0 V and VDD.
7 VSS power_in Ground reference pin at 0 V (VSS), to which all voltages are referenced.
8 3A input Data input A of NOR gate 3; unused inputs must be tied to VDD, VSS or another input, and input voltage must stay between 0 V and VDD.
9 3B input Data input B of NOR gate 3; unused inputs must be tied to VDD, VSS or another input, and input voltage must stay between 0 V and VDD.
10 3Y output Output of NOR gate 3, which is fully buffered for high noise immunity and pattern insensitivity.
11 4Y output Output of NOR gate 4, which is fully buffered for high noise immunity and pattern insensitivity.
12 4A input Data input A of NOR gate 4; unused inputs must be tied to VDD, VSS or another input, and input voltage must stay between 0 V and VDD.
13 4B input Data input B of NOR gate 4; unused inputs must be tied to VDD, VSS or another input, and input voltage must stay between 0 V and VDD.
14 VDD power_in Positive supply pin; the recommended operating range is 3 V to 15 V referenced to VSS, and the absolute maximum supply is 18 V.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute maximum) VDD -0.5 18 V 3
Input clamp current IIK -10 10 mA VI<-0.5 或 VI>VDD+0.5V 3
Input voltage (absolute maximum, max printed as VDD+0.5) VI -0.5 V 3
Output clamp current IOK -10 10 mA VO<-0.5 或VO>VDD+0.5V 3
Input/output current II/O -10 10 mA 3
Supply current IDD 50 mA 3
Storage temperature Tstg -65 150 ℃ 3
Operating ambient temperature (absolute maximum) Tamb -40 85 ℃ 3
Soldering temperature TL 260 ℃ 10 秒 3
Supply voltage (recommended operating) VDD 3 15 V 3
Input voltage (recommended, max printed as VDD) VI 0 V 3
Ambient temperature (recommended operating) Tamb -40 85 ℃ 3
High-level input voltage VIH 3.5 V VDD=5V, /Io/<1uA 4
High-level input voltage VIH 7 V VDD=10V 4
High-level input voltage VIH 11 V VDD=15V 4
Low-level input voltage VIL 1.5 V VDD=5V, /Io/<1uA 4
Low-level input voltage VIL 3 V VDD=10V 4
Low-level input voltage VIL 4 V VDD=15V 4
High-level output voltage VOH 4.95 V VDD=5V, /Io/<1uA 4
High-level output voltage VOH 9.95 V VDD=10V 4
High-level output voltage VOH 14.95 V VDD=15V 4
Low-level output voltage VOL 0.05 V VDD=5V, /Io/<1uA 4
High-level output current IOH -1.4 mA VDD=5V VO=2.5V 4
High-level output current IOH -0.5 mA VDD=5V VO=4.6V 4
High-level output current IOH -1.3 mA VDD=10V VO=9.5V 4
High-level output current IOH -3.4 mA VDD=15V VO=13.5V 4
Low-level output current IOL 0.5 mA VDD=5V VO=0.4V 4
Low-level output current IOL 1.3 mA VDD=10V VO=0.5V 4
Low-level output current IOL 3.4 mA VDD=15V VO=1.5V 4
Input leakage current II -0.1 0.1 uA VDD=15V 4
Quiescent supply current IDD 0.25 uA VDD=5V,输入接 VDD 或 VSS 4
Quiescent supply current IDD 0.5 uA VDD=10V,输入接 VDD 或 VSS 4
Quiescent supply current IDD 1 uA VDD=15V,输入接 VDD 或 VSS 4
Input capacitance CI 7.5 pF 4
Propagation delay time (1st group, tPHL) tPHL 60 10 ns VDD=5V 5
Propagation delay time (1st group, tPHL) tPHL 25 50 ns VDD=1V 5
Propagation delay time (1st group, tPHL) tPHL 20 40 ns VDD=1V 5
Propagation delay time (2nd group, tPHL) tPHL 50 10 ns VDD=5V 5
Propagation delay time (2nd group, tPHL) tPHL 25 45 ns VDD=1V 5
Propagation delay time (2nd group, tPHL) tPHL 20 35 ns VDD=1V 5
Transition time (3rd group, tPHL) tPHL 60 120 ns VDD=5V 5
Transition time (3rd group, tPHL) tPHL 30 60 ns VDD=1V 5
Transition time (3rd group, tPHL) tPHL 20 40 ns VDD=1V 5
Transition time (4th group, tPHL) tPHL 60 120 ns VDD=5V 5
Transition time (4th group, tPHL) tPHL 30 60 ns VDD=1V 5
Transition time (4th group, tPHL) tPHL 20 40 ns VDD=1V 5

CAD (KiCad official)

  • Symbol: CD4001BMT
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4001bmt-etched.step / cd4001bmt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4001bmt.step / cd4001bmt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (10 pp, sha256 ec7cae28195d841f, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF