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CD4001BM96

Public Made by Adom

by adom

Texas Instruments Gates, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs cd4001bm96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cd4001bm96: viewers · Ray
cd4001bm96-etched.fit.json cd4001bm96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd4001bm96-etched.glb cd4001bm96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
cd4001bm96-etched.step cd4001bm96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
cd4001bm96.glb Publish 0.1.0 · Ray
cd4001bm96.kicad_mod Publish 0.1.0 · Ray
cd4001bm96.kicad_sym Publish 0.1.0 · Ray
cd4001bm96.lbr Publish 0.1.0 · Ray
cd4001bm96.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
page.json cd4001bm96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
README.md cd4001bm96: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

CD4001BM96

Texas Instruments · Gates · SOIC-14

CD4001BM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A. CMOS logic input to first NOR gate (TI label 'A'). Input current max 1 uA at 18 V.
2 1B input Gate 1 input B. CMOS logic input to first NOR gate (TI label 'B').
3 1Y output Gate 1 output J = NOT(A+B). Buffered CMOS output; symmetrical source/sink drive per DC electrical characteristics.
4 2Y output Gate 2 output K = NOT(C+D). Buffered CMOS output.
5 2A input Gate 2 input C. CMOS logic input to second NOR gate.
6 2B input Gate 2 input D. CMOS logic input to second NOR gate.
7 VSS power_in Negative supply / ground reference. All voltages referenced to VSS terminal.
8 3A input Gate 3 input E. CMOS logic input to third NOR gate.
9 3B input Gate 3 input F. CMOS logic input to third NOR gate.
10 3Y output Gate 3 output L = NOT(E+F). Buffered CMOS output.
11 4Y output Gate 4 output M = NOT(G+H). Buffered CMOS output.
12 4A input Gate 4 input G. CMOS logic input to fourth NOR gate.
13 4B input Gate 4 input H. CMOS logic input to fourth NOR gate.
14 VDD power_in Positive supply. Recommended operating range 3 V to 18 V; absolute max 20 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • CD4001BM96
  • CD4001BM96E4
  • CD4001BM96G4
  • CD4001BMG4
  • CD4001BMT
  • CD4001BE
  • CD4001BEE4
  • CD4001BF
  • CD4001BF3A
  • CD4001BNSR
  • CD4001BNSRG4
  • CD4001BPW
  • CD4001BPWR
  • CD4001BPWRG4

CAD (KiCad official)

  • Symbol: CD4001BM96
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd4001bm96-etched.step / cd4001bm96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4001bm96.step / cd4001bm96.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
cd4001bm96.step 195 KB You want the bare part, or you mark your own boards.
cd4001bm96-etched.step 2.6 MB You want the part with CD4001BM96 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 639 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (18 pp, sha256 25b2bd3da17ee3f5, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF