component
CD4001BE
Public Made by Adomby adom
Texas Instruments Logic Gates, DIP-14. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
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CD4001BE
Texas Instruments · Logic Gates · DIP-14
CD4001BE from Texas Instruments, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN1A | input | Gate 1 input 1 of the 2-input NOR gate, protected by the CMOS input network and limited to -0.5V to VDD+0.5V. |
| 2 | IN1B | input | Gate 1 input 2 of the 2-input NOR gate, protected by the CMOS input network and limited to -0.5V to VDD+0.5V. |
| 3 | OUT1 | output | Gate 1 NOR output, the inverted OR of pins 1 and 2. |
| 4 | OUT2 | output | Gate 2 NOR output, the inverted OR of pins 5 and 6. |
| 5 | IN2B | input | Gate 2 input 2 of the 2-input NOR gate, limited to -0.5V to VDD+0.5V. |
| 6 | IN2A | input | Gate 2 input 1 of the 2-input NOR gate, limited to -0.5V to VDD+0.5V. |
| 7 | VSS | power_in | Ground (VSS) supply terminal, the reference for all voltage ratings. |
| 8 | IN3A | input | Gate 3 input 1 of the 2-input NOR gate, limited to -0.5V to VDD+0.5V. |
| 9 | IN3B | input | Gate 3 input 2 of the 2-input NOR gate, limited to -0.5V to VDD+0.5V. |
| 10 | OUT3 | output | Gate 3 NOR output, the inverted OR of pins 8 and 9. |
| 11 | OUT4 | output | Gate 4 NOR output, the inverted OR of pins 12 and 13. |
| 12 | IN4B | input | Gate 4 input 2 of the 2-input NOR gate, limited to -0.5V to VDD+0.5V. |
| 13 | IN4A | input | Gate 4 input 1 of the 2-input NOR gate, limited to -0.5V to VDD+0.5V. |
| 14 | VDD | power_in | Positive supply, recommended 3V to 18V and absolute maximum -0.5V to +20V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | DIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature range | -55 | 125 | °C | Op temp for CD4001BE (PDIP-14, N package), from packaging addendum | 5 |
CAD (KiCad official)
- Symbol:
CD4001BE - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files:
cd4001be-etched.step/cd4001be-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4001be.step/cd4001be.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
29898c1b5c0da39b, retrieved 2026-10-21, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD4001BE
**Texas Instruments** · Logic Gates · DIP-14
CD4001BE from Texas Instruments, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN1A | input | Gate 1 input 1 of the 2-input NOR gate, protected by the CMOS input network and limited to -0.5V to VDD+0.5V. |
| 2 | IN1B | input | Gate 1 input 2 of the 2-input NOR gate, protected by the CMOS input network and limited to -0.5V to VDD+0.5V. |
| 3 | OUT1 | output | Gate 1 NOR output, the inverted OR of pins 1 and 2. |
| 4 | OUT2 | output | Gate 2 NOR output, the inverted OR of pins 5 and 6. |
| 5 | IN2B | input | Gate 2 input 2 of the 2-input NOR gate, limited to -0.5V to VDD+0.5V. |
| 6 | IN2A | input | Gate 2 input 1 of the 2-input NOR gate, limited to -0.5V to VDD+0.5V. |
| 7 | VSS | power_in | Ground (VSS) supply terminal, the reference for all voltage ratings. |
| 8 | IN3A | input | Gate 3 input 1 of the 2-input NOR gate, limited to -0.5V to VDD+0.5V. |
| 9 | IN3B | input | Gate 3 input 2 of the 2-input NOR gate, limited to -0.5V to VDD+0.5V. |
| 10 | OUT3 | output | Gate 3 NOR output, the inverted OR of pins 8 and 9. |
| 11 | OUT4 | output | Gate 4 NOR output, the inverted OR of pins 12 and 13. |
| 12 | IN4B | input | Gate 4 input 2 of the 2-input NOR gate, limited to -0.5V to VDD+0.5V. |
| 13 | IN4A | input | Gate 4 input 1 of the 2-input NOR gate, limited to -0.5V to VDD+0.5V. |
| 14 | VDD | power_in | Positive supply, recommended 3V to 18V and absolute maximum -0.5V to +20V referenced to VSS. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | DIP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature range | | -55 | | 125 | °C | Op temp for CD4001BE (PDIP-14, N package), from packaging addendum | 5 |
## CAD (KiCad official)
- Symbol: `CD4001BE`
- Footprint: `Package_DIP:DIP-14_W7.62mm`
- 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files: `cd4001be-etched.step` / `cd4001be-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4001be.step` / `cd4001be.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd4001b) (23 pp, sha256 `29898c1b5c0da39b`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd4001be-datasheet.pdf)