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CAD + datasheet + .step

Ray ·1abba00257 ·2mo ago ·parent 8a4d585
1 file changed +155−8
page.json+155−8
@@ -1,8 +1,11 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "cd4001",+  "title": "CD4001B Quad NOR Gate",+  "brief": "Quad NOR Gate in the 4000B CMOS family, 3 V to 18 V.",   "version": "0.1.0",-  "type": "component",-  "description": "Quad NOR Gate in the 4000B CMOS family, 3 V to 18 V.",+  "license": "CC-BY-SA-4.0",   "tags": [     "logic",     "-gate",@@ -11,6 +14,155 @@     "ti",     "soic-14"   ],+  "component": {+    "mpn": "CD4001B",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Logic Gate",+    "datasheet": "https://www.ti.com/lit/ds/symlink/cd4001b.pdf",+    "parts": {+      "symbol": "cd4001.kicad_sym",+      "footprint": "cd4001.kicad_mod",+      "model_3d": "cd4001.glb",+      "model_3d_step": "cd4001.step"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "A",+        "type": "input",+        "description": "Gate 1 input A (J = A NOR B). CMOS input, high impedance, protected by input protection network. VIH min 3.5 V @ VDD=5 V."+      },+      {+        "number": "2",+        "name": "B",+        "type": "input",+        "description": "Gate 1 input B (J = A NOR B). CMOS input, high impedance, protected by input protection network."+      },+      {+        "number": "3",+        "name": "J",+        "type": "output",+        "description": "Gate 1 output: J = A NOR B. Buffered CMOS output; IOH \u2248 \u22121 mA / IOL \u2248 1 mA min @ VDD=10 V."+      },+      {+        "number": "4",+        "name": "K",+        "type": "output",+        "description": "Gate 2 output: K = C NOR D. Buffered CMOS output."+      },+      {+        "number": "5",+        "name": "C",+        "type": "input",+        "description": "Gate 2 input C (K = C NOR D). CMOS input, high impedance."+      },+      {+        "number": "6",+        "name": "D",+        "type": "input",+        "description": "Gate 2 input D (K = C NOR D). CMOS input, high impedance."+      },+      {+        "number": "7",+        "name": "VSS",+        "type": "power_in",+        "description": "Negative supply / ground reference. Typically 0 V. All input/output voltages referenced to VSS."+      },+      {+        "number": "8",+        "name": "E",+        "type": "input",+        "description": "Gate 3 input E (L = E NOR F). CMOS input, high impedance."+      },+      {+        "number": "9",+        "name": "F",+        "type": "input",+        "description": "Gate 3 input F (L = E NOR F). CMOS input, high impedance."+      },+      {+        "number": "10",+        "name": "L",+        "type": "output",+        "description": "Gate 3 output: L = E NOR F. Buffered CMOS output."+      },+      {+        "number": "11",+        "name": "M",+        "type": "output",+        "description": "Gate 4 output: M = G NOR H. Buffered CMOS output."+      },+      {+        "number": "12",+        "name": "G",+        "type": "input",+        "description": "Gate 4 input G (M = G NOR H). CMOS input, high impedance."+      },+      {+        "number": "13",+        "name": "H",+        "type": "input",+        "description": "Gate 4 input H (M = G NOR H). CMOS input, high impedance."+      },+      {+        "number": "14",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive supply voltage. Recommended 3 V to 18 V (absolute max \u22120.5 V to +20 V referenced to VSS). Bypass with 0.1 \u00b5F ceramic to VSS."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/cd4001b.pdf",+        "pages": 23,+        "sha256": "d33d12a8e68dd293",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Type": "Quad NOR Gate",+      "Logic family": "4000B (CMOS)",+      "Supply voltage": "3 V to 18 V",+      "Propagation delay": "45 ns typ at 10 V",+      "Operating temperature": "-55 C to 125 C"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "NOR gate",+    "CMOS logic",+    "wide-voltage logic",+    "glue logic"+  ],+  "discovery_pitch": "The CD4001B contains four independent 2-input NOR gates in the 4000B CMOS family; each output is high only when both inputs are low.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -27,10 +179,5 @@     "docs/cd4001-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file