# CD14538BM

**Texas Instruments** · Pre-ordered Chips · SOP-16

CD14538BM from Texas Instruments, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Cx1 | passive | External timing capacitor terminal for monostable 1, electrically connected internally with terminals 8 and 15 per the datasheet note. |
| 2 | Rx Cx(1) | passive | Common external timing resistor/capacitor junction for monostable 1; Rx minimum is 4 kΩ and Cx range is 0 pF to 100 µF, with T = RxCx. |
| 3 | RESET(1) | input | Active-low reset for monostable 1 that immediately terminates the output pulse; tie to VDD if unused. |
| 4 | +TR(1) | input | Leading-edge (rising) trigger input of monostable 1 with Schmitt-trigger input; tie to VSS if unused. |
| 5 | -TR(1) | input | Trailing-edge (falling) trigger input of monostable 1 with Schmitt-trigger input; tie to VDD if unused. |
| 6 | Q1 | output | Buffered Q output of monostable 1. |
| 7 | Q1̅ | output | Buffered complementary Q-bar output of monostable 1. |
| 8 | VSS | power_in | Ground/negative supply terminal, electrically connected internally with terminals 1 and 15. |
| 9 | Q2̅ | output | Buffered complementary Q-bar output of monostable 2. |
| 10 | Q2 | output | Buffered Q output of monostable 2. |
| 11 | -TR(2) | input | Trailing-edge (falling) trigger input of monostable 2 with Schmitt-trigger input; tie to VDD if unused. |
| 12 | +TR(2) | input | Leading-edge (rising) trigger input of monostable 2 with Schmitt-trigger input; tie to VSS if unused. |
| 13 | RESET(2) | input | Active-low reset for monostable 2 that immediately terminates the output pulse; tie to VDD if unused. |
| 14 | Rx Cx(2) | passive | Common external timing resistor/capacitor junction for monostable 2; Rx minimum is 4 kΩ and Cx range is 0 pF to 100 µF, with T = RxCx. |
| 15 | Cx2 | passive | External timing capacitor terminal for monostable 2, electrically connected internally with terminals 1 and 8 per the datasheet note. |
| 16 | VDD | power_in | Positive supply terminal; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOP-16 |
| Category | Interface ICs |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `CD14538BM`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `cd14538bm-etched.step` / `cd14538bm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd14538bm.step` / `cd14538bm.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd14538bm.pdf) (24 pp, sha256 `2b382f6ad28a94bf`, retrieved 2026-10-22, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd14538bm-datasheet.pdf)