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CD14538BE

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Texas Instruments Monostable Multivibrators, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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CD14538BE

Texas Instruments · Monostable Multivibrators · DIP-16

CD14538BE from Texas Instruments, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CX1 passive External timing capacitor terminal for MONO1; one end of CX connects here, other end to RC1 (pin 2); minimum CX = 5000 pF per datasheet note.
2 RC1 passive Timing resistor/capacitor junction for MONO1; external RX connects from VDD to this pin and CX connects from this pin to CX1 (pin 1); minimum RX = 4 KΩ; pulse width T = RX × CX.
3 ~{RESET1} input Active-low asynchronous reset for MONO1; when asserted low immediately terminates the Q output pulse regardless of trigger state; tie to VDD when not used.
4 +TR1 input Leading-edge (positive) trigger input for MONO1; initiates output pulse on rising edge when -TR1 (pin 5) is held low; minimum input pulse width 140 ns at VDD = 5V.
5 -TR1 input Trailing-edge (negative) trigger input for MONO1; initiates output pulse on falling edge when +TR1 (pin 4) is held high; minimum input pulse width 140 ns at VDD = 5V; tie to VDD when using leading-edge mode.
6 Q1 output Non-inverting output of MONO1; drives high for pulse width T = RX × CX after triggering; output high source current 1 mA min at VDD = 5V, 3.2 mA min at VDD = 10V.
7 ~{Q1} output Inverting complement output of MONO1; drives low for the duration of pulse width T; complementary to Q1 (pin 6) at all times.
8 VSS power_in Negative supply (ground) reference, 0 V; all voltages referenced to this terminal.
9 ~{Q2} output Inverting complement output of MONO2; drives low for the duration of pulse width T; complementary to Q2 (pin 10) at all times.
10 Q2 output Non-inverting output of MONO2; drives high for pulse width T = RX × CX after triggering; output high source current 1 mA min at VDD = 5V, 3.2 mA min at VDD = 10V.
11 -TR2 input Trailing-edge (negative) trigger input for MONO2; initiates output pulse on falling edge when +TR2 (pin 12) is held high; minimum input pulse width 140 ns at VDD = 5V.
12 +TR2 input Leading-edge (positive) trigger input for MONO2; initiates output pulse on rising edge when -TR2 (pin 11) is held low; minimum input pulse width 140 ns at VDD = 5V.
13 ~{RESET2} input Active-low asynchronous reset for MONO2; when asserted low immediately terminates the Q output pulse regardless of trigger state; tie to VDD when not used.
14 RC2 passive Timing resistor/capacitor junction for MONO2; external RX connects from VDD to this pin and CX connects from this pin to CX2 (pin 15); minimum RX = 4 KΩ; pulse width T = RX × CX.
15 CX2 passive External timing capacitor terminal for MONO2; one end of CX connects here, other end to RC2 (pin 14); minimum CX = 5000 pF per datasheet note.
16 VDD power_in Positive supply voltage; recommended operating range 3V to 18V (full temperature range), absolute maximum 20V; quiescent current 100 µA max at VDD = 18V, 25°C.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package DIP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD14538BE
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd14538be-etched.step / cd14538be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd14538be.step / cd14538be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (22 pp, sha256 e1f0669c091291a1, retrieved 2026-09-29, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF