component

CC6920SO-5A

Public Made by Adom

by adom

Cross chip Current Sensors, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs cc6920so-5a: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
cc6920so-5a-etched.fit.json cc6920so-5a: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
cc6920so-5a-etched.glb cc6920so-5a: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
cc6920so-5a-etched.step cc6920so-5a: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
cc6920so-5a.glb Publish 0.1.0 · Ray 1mo ago
cc6920so-5a.kicad_mod Publish 0.1.0 · Ray 1mo ago
cc6920so-5a.kicad_sym Publish 0.1.0 · Ray 1mo ago
cc6920so-5a.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 8 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
cc6920so-5a.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 11d ago
README.md cc6920so-5a: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 18d ago

CC6920SO-5A

Cross chip · Current Sensors · SOP-8

CC6920SO-5A from Cross chip, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IP+ passive Primary current input (positive terminal). Internally tied to pin 2 through the low-resistance (0.9 mΩ typ) integrated copper conductor. Current flows from IP+ (pins 1-2) to IP- (pins 3-4) for a positive reading. Isolated from the signal side by 3500 Vrms.
2 IP+ passive Primary current input (positive terminal), second lead of the IP+ side of the integrated copper conductor. Must be paralleled with pin 1 on the PCB.
3 IP- passive Primary current output (negative terminal), first lead of the IP- side of the integrated copper conductor. Must be paralleled with pin 4 on the PCB.
4 IP- passive Primary current output (negative terminal), second lead of the IP- side of the integrated copper conductor. Must be paralleled with pin 3 on the PCB.
5 GND power_in Signal-side ground reference for VCC, VOUT, and VZCR. Isolated from the primary current path (IP+/IP-) by 3500 Vrms (basic isolation 424 Vrms).
6 VZCR output Zero-current reference signal output (typically VCC/2). Source current up to 400 µA, sink current up to 3 mA; recommended design margin keeps IZCR < 0.4 mA (reserve ~0.3 mA). Used as a stable reference for downstream difference amplifiers.
7 OUT output Analog voltage output proportional to primary current. For the 5A variant: VOUT = VCC/2 + 0.400 × IP(A). Zero-current output = VCC/2 (2.490-2.510 V at VCC=5V). Linear range 0.5-4.5 V, source current 6 mA / sink 30 mA max, drives up to 1 nF load with ≥1.5 kΩ pull.
8 VCC power_in Analog supply, 4.5-5.5 V (5 V typ), 20 mA typ / 25 mA max quiescent. Absolute maximum 7 V. Decouple with a 0.1 µF ceramic to GND close to the pin.

Key specifications

Parameter Value
Manufacturer Cross chip
Package SOP-8
Category Sensor
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • CC6920SO-2.5A
  • CC6920SO-5A
  • CC6920SO-10A
  • CC6920SO-20A
  • CC6920SO-25A
  • CC6920SO-30A
  • CC6920SO-40A
  • CC6920SO-50A
  • CC6920SO-XXA

CAD (KiCad official)

  • Symbol: CC6920SO-5A
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: cc6920so-5a-etched.step / cc6920so-5a-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cc6920so-5a.step / cc6920so-5a.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
cc6920so-5a.step 122 KB You want the bare part, or you mark your own boards.
cc6920so-5a-etched.step 2.5 MB You want the part with CC6920SO-5A already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 596 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cross chip datasheet (23 pp, sha256 5fe4aa3fee763407, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF