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Name Last commit message Last updated
docs cc6920bso-5a: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
cc6920bso-5a-etched.fit.json cc6920bso-5a: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
cc6920bso-5a-etched.glb cc6920bso-5a: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
cc6920bso-5a-etched.step cc6920bso-5a: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
cc6920bso-5a.glb Publish 0.1.0 · Ray 1mo ago
cc6920bso-5a.kicad_mod Publish 0.1.0 · Ray 1mo ago
cc6920bso-5a.kicad_sym Publish 0.1.0 · Ray 1mo ago
cc6920bso-5a.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 8 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
cc6920bso-5a.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 11d ago
README.md cc6920bso-5a: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 18d ago

CC6920BSO-5A

Cross chip · Current Sensors · SOP-8

CC6920BSO-5A from Cross chip, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IP+ passive Current sampled + (primary conductor input). Tied to pin 2 internally; connect both pins 1 and 2 to the positive side of the sensed current path. Rated up to 40 A continuous and 100 A peak (3 s).
2 IP+ passive Current sampled + (primary conductor input). Tied to pin 1 internally; connect both pins 1 and 2 to the positive side of the sensed current path.
3 IP- passive Current sampled - (primary conductor return). Tied to pin 4 internally; connect both pins 3 and 4 to the return side of the sensed current path. Basic working isolation to secondary is 424 VRMS with 3500 VRMS withstand.
4 IP- passive Current sampled - (primary conductor return). Tied to pin 3 internally; connect both pins 3 and 4 to the return side of the sensed current path.
5 GND power_in Signal ground reference for the secondary (Hall-sensor) circuitry. All output voltages (VOUT, VZCR) are referenced to this pin.
6 VZCR output Zero-current reference signal output, nominally VCC/2 (typ. 1.65 V at VCC=3.3 V). Can be used as a ratiometric reference for a downstream ADC or differential amplifier. Source capability ≤ 400 µA, sink ≤ 3 mA - keep load light.
7 OUT output Analog voltage output proportional to sensed primary current. Quiescent (IP=0) output is 50% VCC (1.65 V at VCC=3.3 V). For the -5A variant, sensitivity is typ. 264 mV/A and the linear output swing is 0.2 V to 4.8 V. Load: RL ≥ 1.5 kΩ, CL ≤ 1 nF; source ≤ 6 mA, sink ≤ 30 mA.
8 VCC power_in Power supply for the Hall sensor secondary circuit. Recommended 3.0-3.6 V (typ. 3.3 V); absolute max 7 V. Typical supply current ICC = 20 mA (max 25 mA) with OUT floated. Bypass with a 0.1 µF ceramic to GND close to the pin.

Key specifications

Parameter Value
Manufacturer Cross chip
Package SOP-8
Category Sensor
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • CC6920BSO-5A
  • CC6920BSO-2.5A
  • CC6920BSO-10A
  • CC6920BSO-20A
  • CC6920BSO-25A
  • CC6920BSO-30A
  • CC6920BSO-40A
  • CC6920BSO-50A
  • CC6920BSO-5ASO-XXA

CAD (KiCad official)

  • Symbol: CC6920BSO-5A
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: cc6920bso-5a-etched.step / cc6920bso-5a-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cc6920bso-5a.step / cc6920bso-5a.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
cc6920bso-5a.step 122 KB You want the bare part, or you mark your own boards.
cc6920bso-5a-etched.step 2.8 MB You want the part with CC6920BSO-5A already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 651 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cross chip datasheet (23 pp, sha256 bf0f27c31807521e, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF