Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

CC6905S8-5FB005

Cross chip · Current Sensors · SOP-8

CC6905S8-5FB005 from Cross chip, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IP+ passive Current-sampled positive terminal of the internal copper conductor; pins 1-4 are isolated from pins 5-8 to 100 VRMS (50/60 Hz, 1 min).
2 IP+ passive Current-sampled positive terminal of the internal copper conductor; pins 1-4 are isolated from pins 5-8 to 100 VRMS (50/60 Hz, 1 min).
3 IP- passive Current-sampled negative terminal of the internal copper conductor; pins 1-4 are isolated from pins 5-8 to 100 VRMS (50/60 Hz, 1 min).
4 IP- passive Current-sampled negative terminal of the internal copper conductor; pins 1-4 are isolated from pins 5-8 to 100 VRMS (50/60 Hz, 1 min).
5 GND power_in Ground reference for the sensor circuit, isolated from the IP pins (1-4) to 100 VRMS.
6 VREF power_in Built-in reference voltage output that sets the VOUT quiescent level; the datasheet also offers an external VREF input option with VOUT consistent with it, and no numeric limit is given for this pin.
7 VOUT output Single-ended analog output voltage, limited to VCC + 0.3 V with a source current of at most 25 mA (absolute maximum ratings).
8 VCC power_in Supply voltage input with an absolute maximum rating of 6.5 V.

Key specifications

Parameter Value
Manufacturer Cross chip
Package SOP-8
Category Magnetic Sensors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power Supply Voltage VCC 4.5 5 5.5 V Supply Section, VCC=5V 6
Quiescent Current ICC 10 12 14 mA Supply Section, VCC=5V 6
VREF Output Voltage VREF 2.45 2.5 2.55 V 5V bidirectional Nominal Supply Voltage Series 6
VREF Input Voltage VREFIN 0 4 V VREF input voltage range 6
Output Voltage Operating Range (bidirectional, 5V) VOOR -2 2 V VCC 5V, bidirectional; printed as ±2 45
VREF Nominal Value Error (VREF output mode) VOE 5 mV Built-in VREF output mode, after factory programming 42
Room Temperature Error -1 1 % Room temperature; printed as ±1% 1
Sensitivity Temperature Drift -2.5 2.5 % Sensitivity temperature drift; printed as up to ±2.5% 1
Power Supply Voltage (absolute maximum) VCC 6.5 V 5
Output Source Current IOUT(SOURCE) 25 mA 5
Operating Ambient Temperature TA 125 °C 5
Junction Temperature TJ 165 °C 5
Storage Temperature TS 150 °C 5
Electrostatic Discharge Voltage HBM ESD HBM 4 kV HBM 5
Electrostatic Discharge Voltage CDM ESD CDM 1 kV CDM 5
Latch Up LU 200 mA 5
Withstand Isolation Voltage VISO 100 VRMS 50/60Hz, 1min 5
Withstand Isolation Voltage VISO 150 VRMS t = 1s 5
Clearance (IP leads to signal leads, SOP8) Dcl 4.3 mm Minimum distance through air from IP leads to signal leads, SOP8 5
Creepage (IP wire to signal wire, SOP8) Dcr 4.3 mm Minimum distance along the package from IP wire to signal wire, SOP8 5
Quiescent Output Voltage VOQ 2.5 V 5V bidirectional series, IP=0A, VREF output mode 43
Sensitivity 400 mV/A CC6905S8-5FB005, 5V, -5A to +5A, VREF output mode 43

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper foil 400mm2 connected to IP pins, each layer of copper foils connected by over-hole. Test environment: open environment, quiescent air Package Thermography Package Thermography 47

CAD (KiCad official)

  • Symbol: CC6905S8-5FB005
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: cc6905s8-5fb005-etched.step / cc6905s8-5fb005-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cc6905s8-5fb005.step / cc6905s8-5fb005.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cross chip datasheet (56 pp, sha256 86071652e648b8e7, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF