component

CC6900SO-30A

Public Made by Adom

by adom

Cross chip Current Sensors, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs cc6900so-30a: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
cc6900so-30a-etched.fit.json cc6900so-30a: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
cc6900so-30a-etched.glb cc6900so-30a: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
cc6900so-30a-etched.step cc6900so-30a: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
cc6900so-30a.glb Publish 0.1.0 · Ray 1mo ago
cc6900so-30a.kicad_mod Publish 0.1.0 · Ray 1mo ago
cc6900so-30a.kicad_sym Publish 0.1.0 · Ray 1mo ago
cc6900so-30a.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 8 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
cc6900so-30a.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 11d ago
README.md cc6900so-30a: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 18d ago

CC6900SO-30A

Cross chip · Current Sensors · SOP-8

CC6900SO-30A from Cross chip, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IP+ passive Primary sampled current positive terminal. Tied internally to pin 2 as one end of the low-impedance primary current conductor. 100 V isolation to signal-side pins.
2 IP+ passive Primary sampled current positive terminal (paralleled with pin 1). Part of the internal low-impedance primary conductor whose magnetic field is sensed by the on-die Hall element.
3 IP- passive Primary sampled current negative terminal. Tied internally to pin 4 as the return end of the primary current conductor.
4 IP- passive Primary sampled current negative terminal (paralleled with pin 3).
5 GND power_in Signal-side ground reference for the internal Hall amplifier and output stage.
6 NC unconnected No connect. Datasheet specifies this pin must be left floating (需悬空).
7 OUT output Analog signal output. Quiescent output = 50% VCC in zero magnetic field; swings linearly from 0.5 V to 4.5 V at VCC = 5 V. For the -30A variant, sensitivity is 67 mV/A.
8 VCC power_in Supply voltage input, nominal 5 V. Powers the Hall front-end, chopper-stabilized amplifier, oscillator and output driver.

Key specifications

Parameter Value
Manufacturer Cross chip
Package SOP-8
Category Sensor
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • CC6900SO-30A
  • CC6900SO-30ASO-5A
  • CC6900SO-30ASO-10A
  • CC6900SO-30ASO-20A

CAD (KiCad official)

  • Symbol: CC6900SO-30A
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: cc6900so-30a-etched.step / cc6900so-30a-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cc6900so-30a.step / cc6900so-30a.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
cc6900so-30a.step 122 KB You want the bare part, or you mark your own boards.
cc6900so-30a-etched.step 2.9 MB You want the part with CC6900SO-30A already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 675 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cross chip datasheet (3 pp, sha256 e459878df789bbd5, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF