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CC430F6126IRGCR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CC430F6126IRGCR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · QFN-64-EP(9x9)

CC430F6126IRGCR from Texas Instruments, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.7/PM_UCA0CLK/PM_UCB0STE/R03 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function (default USCI_A0 clock input/output, USCI_B0 SPI slave transmit enable), also LCD analog voltage port R03 (V5).
2 P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF bidirectional General-purpose digital I/O with port interrupt and mappable secondary function (default USCI_A0 UART transmit data and SPI slave in master out), also LCD analog voltage port R13 (V3 or V4) and external reference input LCDREF for the regulated LCD voltage.
3 P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function (default USCI_A0 UART receive data and SPI slave out master in), also LCD analog voltage port R23 (V2).
4 LCDCAP/R33 bidirectional LCD capacitor connection and input/output port of the most positive analog LCD voltage (V1); must be connected to VSS if not used.
5 COM0 output LCD common output COM0 for the LCD backplane.
6 P5.7/COM1/S26 bidirectional General-purpose digital I/O, alternatively LCD common output COM1 or LCD segment output S26.
7 P5.6/COM2/S25 bidirectional General-purpose digital I/O, alternatively LCD common output COM2 or LCD segment output S25.
8 P5.5/COM3/S24 bidirectional General-purpose digital I/O, alternatively LCD common output COM3 or LCD segment output S24.
9 P5.4/S23 bidirectional General-purpose digital I/O, alternatively LCD segment output S23.
10 VCORE power_out Regulated core power supply generated for the device core.
11 DVCC power_in Digital power supply; recommended VCC at DVCC and AVCC pins is 1.8 V to 3.6 V with PMMCOREVx = 0 (default after POR).
12 P1.4/PM_UCB0CLK/PM_UCA0STE/S22 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function (default USCI_B0 clock input/output and USCI_A0 SPI slave transmit enable), alternatively LCD segment output S22.
13 P1.3/PM_UCB0SIMO/PM_UCB0SDA/S21 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function (default USCI_B0 SPI slave in master out and I2C data), alternatively LCD segment output S21.
14 P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function (default USCI_B0 SPI slave out master in and I2C clock), alternatively LCD segment output S20.
15 P1.1/PM_RFGDO2/S19 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function (default Radio GDO2 output), alternatively LCD segment output S19.
16 P1.0/PM_RFGDO0/S18 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function (default Radio GDO0 output), alternatively LCD segment output S18.
17 P3.7/PM_SMCLK/S17 bidirectional General-purpose digital I/O with mappable secondary function (default SMCLK output), alternatively LCD segment output S17.
18 P3.6/PM_RFGDO1/S16 bidirectional General-purpose digital I/O with mappable secondary function (default Radio GDO1 output), alternatively LCD segment output S16.
19 P3.5/PM_TA0CCR4A/S15 bidirectional General-purpose digital I/O with mappable secondary function (default TA0 CCR4 compare output or capture input), alternatively LCD segment output S15.
20 P3.4/PM_TA0CCR3A/S14 bidirectional General-purpose digital I/O with mappable secondary function (default TA0 CCR3 compare output or capture input), alternatively LCD segment output S14.
21 P3.3/PM_TA0CCR2A/S13 bidirectional General-purpose digital I/O with mappable secondary function (default TA0 CCR2 compare output or capture input), alternatively LCD segment output S13.
22 P3.2/PM_TA0CCR1A/S12 bidirectional General-purpose digital I/O with mappable secondary function (default TA0 CCR1 compare output or capture input), alternatively LCD segment output S12.
23 P3.1/PM_TA0CCR0A/S11 bidirectional General-purpose digital I/O with mappable secondary function (default TA0 CCR0 compare output or capture input), alternatively LCD segment output S11.
24 P3.0/PM_CBOUT0/PM_TA0CLK/S10 bidirectional General-purpose digital I/O with mappable secondary function (default Comparator_B output and TA0 clock input), alternatively LCD segment output S10.
25 DVCC power_in Digital power supply; recommended VCC at DVCC and AVCC pins is 1.8 V to 3.6 V with PMMCOREVx = 0 (default after POR).
26 P4.7/S9 bidirectional General-purpose digital I/O, alternatively LCD segment output S9.
27 P4.6/S8 bidirectional General-purpose digital I/O, alternatively LCD segment output S8.
28 P4.5/S7 bidirectional General-purpose digital I/O, alternatively LCD segment output S7.
29 P4.4/S6 bidirectional General-purpose digital I/O, alternatively LCD segment output S6.
30 P4.3/S5 bidirectional General-purpose digital I/O, alternatively LCD segment output S5.
31 P4.2/S4 bidirectional General-purpose digital I/O, alternatively LCD segment output S4.
32 P4.1/S3 bidirectional General-purpose digital I/O, alternatively LCD segment output S3.
33 P4.0/S2 bidirectional General-purpose digital I/O, alternatively LCD segment output S2.
34 P5.3/S1 bidirectional General-purpose digital I/O, alternatively LCD segment output S1.
35 P5.2/S0 bidirectional General-purpose digital I/O, alternatively LCD segment output S0.
36 RF_XIN input Input terminal for the RF crystal oscillator, or external clock input.
37 RF_XOUT output Output terminal for the RF crystal oscillator.
38 AVCC_RF power_in Radio analog power supply.
39 AVCC_RF power_in Radio analog power supply.
40 RF_P bidirectional RF I/O: positive RF input to the LNA in receive mode and positive RF output from the PA in transmit mode.
41 RF_N bidirectional RF I/O: negative RF input to the LNA in receive mode and negative RF output from the PA in transmit mode.
42 AVCC_RF power_in Radio analog power supply.
43 AVCC_RF power_in Radio analog power supply.
44 R_BIAS passive External bias resistor for the radio reference current.
45 GUARD power_in Power supply connection for digital noise isolation.
46 PJ.0/TDO bidirectional General-purpose digital I/O; test data output port (JTAG TDO).
47 PJ.1/TDI/TCLK bidirectional General-purpose digital I/O; test data input or test clock input (JTAG TDI/TCLK).
48 PJ.2/TMS bidirectional General-purpose digital I/O; test mode select (JTAG TMS).
49 PJ.3/TCK bidirectional General-purpose digital I/O; test clock (JTAG TCK).
50 TEST/SBWTCK input Test mode pin used to select digital I/O on the JTAG pins; also Spy-Bi-Wire input clock.
51 RST/NMI/SBWTDIO bidirectional Reset input, active low; nonmaskable interrupt input; and Spy-Bi-Wire data input/output.
52 DVCC power_in Digital power supply; recommended VCC at DVCC and AVCC pins is 1.8 V to 3.6 V with PMMCOREVx = 0 (default after POR).
53 AVSS power_in Analog ground supply for ADC12.
54 P5.1/XOUT bidirectional General-purpose digital I/O; output terminal of crystal oscillator XT1 when in crystal mode.
55 P5.0/XIN bidirectional General-purpose digital I/O; input terminal of crystal oscillator XT1.
56 AVCC power_in Analog power supply; recommended VCC at DVCC and AVCC pins is 1.8 V to 3.6 V with PMMCOREVx = 0 (default after POR), and AVCC and DVCC should come from the same source.
57 P2.7/PM_DMAE0/CB7 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function (default DMA external trigger input), also Comparator_B input CB7.
58 P2.6/PM_ACLK/CB6 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function (default ACLK output), also Comparator_B input CB6.
59 P2.5/PM_SVMOUT/CB5 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function (default SVM output), also Comparator_B input CB5.
60 P2.4/PM_RTCCLK/CB4 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function (default RTCCLK output), also Comparator_B input CB4.
61 P2.3/PM_TA1CCR2A/CB3 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function (default TA1 CCR2 compare output or capture input), also Comparator_B input CB3.
62 P2.2/PM_TA1CCR1A/CB2 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function (default TA1 CCR1 compare output or capture input), also Comparator_B input CB2.
63 P2.1/PM_TA1CCR0A/CB1 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function (default TA1 CCR0 compare output or capture input), also Comparator_B input CB1.
64 P2.0/PM_CBOUT1/PM_TA1CLK/CB0 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function (default Comparator_B output and TA1 clock input), also Comparator_B input CB0.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-64-EP(9x9)
Category Embedded Processors & Controllers
Pins 65

CAD (KiCad official)

  • Symbol: CC430F6126IRGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: cc430f6126irgcr-etched.step / cc430f6126irgcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cc430f6126irgcr.step / cc430f6126irgcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (133 pp, sha256 7d64cc73f89fa313, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF