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CC430F5137IRGZR

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Texas Instruments RF Transceiver ICs, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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CC430F5137IRGZR

Texas Instruments · RF Transceiver ICs · QFN-48-EP(7x7)

CC430F5137IRGZR from Texas Instruments, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P2.2/PM_TA1CCR1A/CB2/A2 bidirectional General-purpose digital I/O with port interrupt; default mapping TA1 CCR1 compare output or capture input, Comparator_B input CB2, 12-bit ADC analog input A2.
2 P2.1/PM_TA1CCR0A/CB1/A1 bidirectional General-purpose digital I/O with port interrupt; default mapping TA1 CCR0 compare output or capture input, Comparator_B input CB1, 12-bit ADC analog input A1.
3 P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0 bidirectional General-purpose digital I/O with port interrupt; default mapping Comparator_B output and TA1 clock input, Comparator_B input CB0, 12-bit ADC analog input A0.
4 P1.7/PM_UCA0CLK/PM_UCB0STE bidirectional General-purpose digital I/O with port interrupt; default mapping USCI_A0 clock input/output and USCI_B0 SPI slave transmit enable.
5 P1.6/PM_UCA0TXD/PM_UCA0SIMO bidirectional General-purpose digital I/O with port interrupt; default mapping USCI_A0 UART transmit data and SPI slave in master out.
6 P1.5/PM_UCA0RXD/PM_UCA0SOMI bidirectional General-purpose digital I/O with port interrupt; default mapping USCI_A0 UART receive data and SPI slave out master in.
7 VCORE power_out Regulated core power supply.
8 DVCC power_in Digital power supply.
9 P1.4/PM_UCB0CLK/PM_UCA0STE bidirectional General-purpose digital I/O with port interrupt; default mapping USCI_B0 clock input/output and USCI_A0 SPI slave transmit enable.
10 P1.3/PM_UCB0SIMO/PM_UCB0SDA bidirectional General-purpose digital I/O with port interrupt; default mapping USCI_B0 SPI slave in master out and I2C data.
11 P1.2/PM_UCB0SOMI/PM_UCB0SCL bidirectional General-purpose digital I/O with port interrupt; default mapping USCI_B0 SPI slave out master in and I2C clock.
12 P1.1/PM_RFGDO2 bidirectional General-purpose digital I/O with port interrupt; default mapping Radio GDO2 output.
13 P1.0/PM_RFGDO0 bidirectional General-purpose digital I/O with port interrupt; default mapping Radio GDO0 output.
14 P3.7/PM_SMCLK bidirectional General-purpose digital I/O with mappable secondary function; default mapping SMCLK output.
15 P3.6/PM_RFGDO1 bidirectional General-purpose digital I/O with mappable secondary function; default mapping Radio GDO1 output.
16 P3.5/PM_TA0CCR4A bidirectional General-purpose digital I/O with mappable secondary function; default mapping TA0 CCR4 compare output or capture input.
17 P3.4/PM_TA0CCR3A bidirectional General-purpose digital I/O with mappable secondary function; default mapping TA0 CCR3 compare output or capture input.
18 P3.3/PM_TA0CCR2A bidirectional General-purpose digital I/O with mappable secondary function; default mapping TA0 CCR2 compare output or capture input.
19 P3.2/PM_TA0CCR1A bidirectional General-purpose digital I/O with mappable secondary function; default mapping TA0 CCR1 compare output or capture input.
20 P3.1/PM_TA0CCR0A bidirectional General-purpose digital I/O with mappable secondary function; default mapping TA0 CCR0 compare output or capture input.
21 P3.0/PM_CBOUT0/PM_TA0CLK bidirectional General-purpose digital I/O with mappable secondary function; default mapping Comparator_B output and TA0 clock input.
22 DVCC power_in Digital power supply.
23 P2.7/PM_ADC12CLK/PM_DMAE0 bidirectional General-purpose digital I/O with port interrupt; default mapping ADC12CLK output and DMA external trigger input.
24 P2.6/PM_ACLK bidirectional General-purpose digital I/O with port interrupt; default mapping ACLK output.
25 RF_XIN input Input terminal for RF crystal oscillator, or external clock input.
26 RF_XOUT output Output terminal for RF crystal oscillator.
27 AVCC_RF power_in Radio analog power supply.
28 AVCC_RF power_in Radio analog power supply.
29 RF_P bidirectional Positive RF input to LNA in receive mode and positive RF output from PA in transmit mode.
30 RF_N bidirectional Negative RF input to LNA in receive mode and negative RF output from PA in transmit mode.
31 AVCC_RF power_in Radio analog power supply.
32 AVCC_RF power_in Radio analog power supply.
33 R_BIAS passive External bias resistor for radio reference current.
34 GUARD power_in Power supply connection for digital noise isolation.
35 PJ.0/TDO bidirectional General-purpose digital I/O; test data output port.
36 PJ.1/TDI/TCLK bidirectional General-purpose digital I/O; test data input or test clock input.
37 PJ.2/TMS bidirectional General-purpose digital I/O; test mode select.
38 PJ.3/TCK bidirectional General-purpose digital I/O; test clock.
39 TEST/SBWTCK input Test mode pin selecting digital I/O on JTAG pins; Spy-Bi-Wire input clock.
40 RST/NMI/SBWTDIO bidirectional Active-low reset input, nonmaskable interrupt input, and Spy-Bi-Wire data input/output.
41 DVCC power_in Digital power supply.
42 AVSS power_in Analog ground supply for ADC12.
43 P5.1/XOUT bidirectional General-purpose digital I/O; output terminal of crystal oscillator XT1.
44 P5.0/XIN bidirectional General-purpose digital I/O; input terminal for crystal oscillator XT1.
45 AVCC power_in Analog power supply.
46 P2.5/PM_SVMOUT/CB5/A5/VREF+/VeREF+ bidirectional General-purpose digital I/O with port interrupt; default mapping SVM output, Comparator_B input CB5, ADC input A5, ADC reference output VREF+ or external reference input VeREF+.
47 P2.4/PM_RTCCLK/CB4/A4/VREF-/VeREF- bidirectional General-purpose digital I/O with port interrupt; default mapping RTCCLK output, Comparator_B input CB4, ADC input A4, negative ADC reference terminal VREF-/VeREF-.
48 P2.3/PM_TA1CCR2A/CB3/A3 bidirectional General-purpose digital I/O with port interrupt; default mapping TA1 CCR2 compare output or capture input, Comparator_B input CB3, 12-bit ADC analog input A3.
49 VSS power_in Exposed die attach pad and chip ground; must be connected to a solid ground plane.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-48-EP(7x7)
Category RF And Wireless
Pins 49

CAD (KiCad official)

  • Symbol: CC430F5137IRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: cc430f5137irgzr-etched.step / cc430f5137irgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cc430f5137irgzr.step / cc430f5137irgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (133 pp, sha256 7d64cc73f89fa313, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF