# CC3235SF12RGKR

**Texas Instruments** · RF Transceiver ICs · VQFN-64-EP(9x9)

CC3235SF12RGKR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO10 | bidirectional | General-purpose input or output that can be muxed to I2C_SCL, UART1_TX, SDCARD_CLK and timer functions, with 2/4/6 mA drive and a 10 µA pullup/pulldown. |
| 2 | GPIO11 | bidirectional | General-purpose input or output that can be muxed to I2C_SDA, UART1_RX, SDCARD_CMD and timer functions, and can be selected as a wakeup source. |
| 3 | GPIO12 | bidirectional | General-purpose input or output that can be muxed to McACLK, pVS, I2C_SCL, UART0_TX and GT_CCP03. |
| 4 | GPIO13 | bidirectional | General-purpose input or output that can be muxed to pHS, I2C_SDA, UART0_RX and GT_CCP04, and can be selected as a wakeup source. |
| 5 | GPIO14 | bidirectional | General-purpose input or output that can be muxed to I2C_SCL, GSPI_CLK, pDATA8 and GT_CCP05. |
| 6 | GPIO15 | bidirectional | General-purpose input or output that can be muxed to I2C_SDA, GSPI_MISO, pDATA9 and SDCARD_DATA0. |
| 7 | GPIO16 | bidirectional | General-purpose input or output that can be muxed to GSPI_MOSI, UART1_TX, pDATA10, SDCARD_CLK and GT_CCP07. |
| 8 | GPIO17 | bidirectional | General-purpose input or output that can be muxed to UART1_RX, GSPI_CS, pDATA11 and SDCARD_CMD, and can be selected as a wakeup source. |
| 9 | VDD_DIG1 | passive | Internal digital core voltage. |
| 10 | VIN_IO1 | power_in | I/O power supply, same as the battery voltage (VBAT 2.1 V to 3.6 V) and must be tied to VBAT. |
| 11 | FLASH_SPI_CLK | output | Serial flash interface SPI clock output; TI recommends enabling the internal weak pulldown during LPDS. |
| 12 | FLASH_SPI_DOUT | output | Serial flash interface SPI data output; TI recommends enabling the internal weak pulldown during LPDS. |
| 13 | FLASH_SPI_DIN | input | Serial flash interface SPI data input; TI recommends enabling the internal weak pulldown during LPDS. |
| 14 | FLASH_SPI_CS | output | Serial flash interface SPI chip-select output. |
| 15 | GPIO22 | bidirectional | General-purpose input or output that can be muxed to McAFSX and GT_CCP04. |
| 16 | TDI | bidirectional | JTAG data input, reset default function, muxed with GPIO23, UART1_TX and I2C_SCL. |
| 17 | TDO | bidirectional | JTAG data output, reset default function, muxed with GPIO24, PWM0, UART1_RX and I2C_SDA, and can be a wakeup source. |
| 18 | GPIO28 | bidirectional | General-purpose input or output with no LPDS retention. |
| 19 | TCK | bidirectional | JTAG/SWD clock, reset default function, muxed with GT_PWM03. |
| 20 | TMS | bidirectional | JTAG mode select or SWDIO, reset default function, muxed with GPIO29. |
| 21 | SOP2 | output | Configuration sense-on-power pin that also serves as TCXO enable (GPIO25), requiring a passive pullup or pulldown resistor and use as an output only. |
| 22 | WLAN_XTAL_N | passive | 40-MHz crystal connection, pulled down (grounded) if an external TCXO is used or unused. |
| 23 | WLAN_XTAL_P | passive | 40-MHz crystal connection or TCXO clock input. |
| 24 | VDD_PLL | passive | Internal analog voltage. |
| 25 | LDO_IN2 | power_in | Analog RF supply fed from the analog DC/DC output. |
| 26 | NC | unconnected | No internal connection; leave unconnected. |
| 27 | A_RX | input | RF A-band (5 GHz) receive input. |
| 28 | A_TX | output | RF A-band (5 GHz) transmit output. |
| 29 | GND | power_in | Ground. |
| 30 | GND | power_in | Ground. |
| 31 | RF_BG | bidirectional | RF BG band (2.4 GHz) transmit and receive port. |
| 32 | nRESET | input | Active-low master chip reset input that must never be left floating and must be held low until VBAT is driven and stable. |
| 33 | VDD_PA_IN | power_in | RF power amplifier input supply from the PA DC/DC output. |
| 34 | SOP1 | bidirectional | Configuration sense-on-power input at boot and 5 GHz switch control (A_SC1) output on power-up, with a 69.8k pulldown recommended when used as switch control. |
| 35 | SOP0 | bidirectional | Configuration sense-on-power input at boot and 5 GHz switch control (A_SC2) output on power-up, with a 69.8k pulldown recommended when used as switch control. |
| 36 | LDO_IN1 | power_in | Analog RF supply fed from the analog DC/DC output. |
| 37 | VIN_DCDC_ANA | power_in | Analog DC/DC supply input, same as battery voltage (VBAT 2.1 V to 3.6 V). |
| 38 | DCDC_ANA_SW | passive | Analog DC/DC converter switching node. |
| 39 | VIN_DCDC_PA | power_in | PA DC/DC converter input supply, same as battery voltage (VBAT 2.1 V to 3.6 V). |
| 40 | DCDC_PA_SW_P | passive | PA DC/DC converter positive switching node. |
| 41 | DCDC_PA_SW_N | passive | PA DC/DC converter negative switching node. |
| 42 | DCDC_PA_OUT | power_out | PA DC/DC converter output. |
| 43 | DCDC_DIG_SW | passive | Digital DC/DC converter switching node. |
| 44 | VIN_DCDC_DIG | power_in | Digital DC/DC converter supply input, same as battery voltage (VBAT 2.1 V to 3.6 V). |
| 45 | DCDC_ANA2_SW_P | bidirectional | Analog2 DC/DC converter positive switching node, usable as GPIO31 on the CC3235S only if a supply is provided on pin 47. |
| 46 | DCDC_ANA2_SW_N | passive | Analog2 DC/DC converter negative switching node. |
| 47 | VDD_ANA2 | passive | Analog2 DC/DC output. |
| 48 | VDD_ANA1 | passive | Analog1 power supply fed by the ANA2 DC/DC output. |
| 49 | VDD_RAM | passive | SRAM LDO output. |
| 50 | GPIO0 | bidirectional | General-purpose input or output that can be muxed to UART0_CTS, UART0_RTS, UART1_RTS, McAXR0/1, GT_CCP00 and GSPI_CS. |
| 51 | RTC_XTAL_P | passive | 32.768-kHz crystal connection or external CMOS-level clock input. |
| 52 | RTC_XTAL_N | passive | 32.768-kHz crystal connection, or a 100-kΩ pullup to supply when used as an output-only digital pin (GPIO32). |
| 53 | GPIO30 | bidirectional | General-purpose input or output that can be muxed to UART0_TX, McACLK, McAFSX, GT_CCP05 and GSPI_MISO. |
| 54 | VIN_IO2 | power_in | Chip supply voltage (VBAT 2.1 V to 3.6 V), tied together with VIO. |
| 55 | GPIO1 | bidirectional | General-purpose input or output that can be muxed to UART0_TX, pCLK, UART1_TX and GT_CCP01. |
| 56 | VDD_DIG2 | passive | Internal digital core voltage. |
| 57 | GPIO2 | bidirectional | Analog input (ADC_CH0, 1.5 V max) or general-purpose I/O that can be a wakeup source; digital I/O must be Hi-Z before enabling the ADC switch. |
| 58 | GPIO3 | bidirectional | Analog input (ADC_CH1, 1.5 V max) or general-purpose I/O; digital I/O must be Hi-Z before enabling the ADC switch. |
| 59 | GPIO4 | bidirectional | Analog input (ADC_CH2, 1.5 V max) or general-purpose I/O that can be a wakeup source; digital I/O must be Hi-Z before enabling the ADC switch. |
| 60 | GPIO5 | bidirectional | Analog input (ADC_CH3, 1.5 V max) or general-purpose I/O; digital I/O must be Hi-Z before enabling the ADC switch. |
| 61 | GPIO6 | bidirectional | General-purpose input or output that can be muxed to UART0_RTS, UART0_CTS, UART1_CTS, pDATA4 and GT_CCP06. |
| 62 | GPIO7 | bidirectional | General-purpose input or output that can be muxed to McACLKX, UART1_RTS, UART0_RTS and UART0_TX. |
| 63 | GPIO8 | bidirectional | General-purpose input or output that can be muxed to SDCARD_IRQ, McAFSX and GT_CCP06. |
| 64 | GPIO9 | bidirectional | General-purpose input or output that can be muxed to GT_PWM05, SDCARD_DATA0, McAXR0 and GT_CCP00. |
| 65 | GND_TAB | power_in | Thermal pad and electrical ground. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-64-EP(9x9) |
| Category | RF And Wireless |
| Pins | 65 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VBAT, VIO (shorted to VBAT) |  | 2.1 | 3.3 | 3.6 | V | Direct battery connection, pins 10, 37, 39, 44, 54 | 30 |
| Ambient thermal slew |  | -20 |  | 20 | °C/minute |  | 30 |
| Supply voltage VBAT and VIO pins |  | -0.5 |  | 3.8 | V | Pins 37, 39, 44 | 30 |
| RF pins |  | -0.5 |  | 2.1 | V |  | 30 |
| Analog pins, crystal pins |  | -0.5 |  | 2.1 | V | Pins 22, 23, 51, 52 | 30 |
| Operating temperature | TA | -40 |  | 85 | °C |  | 30 |
| Storage temperature | Tstg | -55 |  | 125 | °C |  | 30 |
| Junction-to-free air thermal resistance | RΘJA |  | 23 |  | °C/W | Junction-to-free air, air flow 0.0051 m/s | 43 |
| Junction-to-case thermal resistance | RΘJC |  | 6.3 |  | °C/W | Junction-to-case | 43 |
| Junction-to-board thermal resistance | RΘJB |  | 2.4 |  | °C/W | Junction-to-board, air flow 0.0051 m/s | 43 |

## CAD (KiCad official)

- Symbol: `CC3235SF12RGKR`
- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`
- 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
- 3D model files: `cc3235sf12rgkr-etched.step` / `cc3235sf12rgkr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cc3235sf12rgkr.step` / `cc3235sf12rgkr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cc3235sf.pdf) (102 pp, sha256 `be1e089cb450b033`, retrieved 2026-11-06, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cc3235sf12rgkr-datasheet.pdf)