component
CC3200R1M2RGC
Public Made by Adomby adom
Texas Instruments RF Transceiver ICs, VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+102@@ -0,0 +1,102 @@+# CC3200R1M2RGC++**Texas Instruments** · RF Transceiver ICs · VQFN-64-EP(9x9)++CC3200R1M2RGC from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GPIO10 | bidirectional | Multiplexed GPIO10 digital I/O (alternates include UART1_TX, SDCARD_CLK, GT_PWM06); non-fail-safe, with 2/4/6 mA configurable drive and 10 µA pull options. |+| 2 | GPIO11 | bidirectional | Multiplexed GPIO11 digital I/O (alternates include pXCLK/XVCLK, SDCARD_CMD, UART1_RX, McAFSX); non-fail-safe, with 2/4/6 mA configurable drive. |+| 3 | GPIO12 | bidirectional | Multiplexed GPIO12 digital I/O (alternates include pVS/VSYNC, I2C_SCL, UART0_TX, GT_CCP03); non-fail-safe, with 2/4/6 mA configurable drive. |+| 4 | GPIO13 | bidirectional | Multiplexed GPIO13 digital I/O (alternates include pHS/HSYNC, I2C_SDA, UART0_RX, GT_CCP04); non-fail-safe, with 2/4/6 mA configurable drive. |+| 5 | GPIO14 | bidirectional | Multiplexed GPIO14 digital I/O (alternates include GSPI_CLK, pDATA8/CAM_D4, I2C_SCL, GT_CCP05); non-fail-safe, with 2/4/6 mA configurable drive. |+| 6 | GPIO15 | bidirectional | Multiplexed GPIO15 digital I/O (alternates include GSPI_MISO, pDATA9/CAM_D5, I2C_SDA, GT_CCP06); non-fail-safe, with 2/4/6 mA configurable drive. |+| 7 | GPIO16 | bidirectional | Multiplexed GPIO16 digital I/O (alternates include GSPI_MOSI, pDATA10/CAM_D6, UART1_TX, GT_CCP07); non-fail-safe, with 2/4/6 mA configurable drive. |+| 8 | GPIO17 | bidirectional | Multiplexed GPIO17 digital I/O (alternates include GSPI_CS, pDATA11/CAM_D7, UART1_RX); non-fail-safe, with 2/4/6 mA configurable drive. |+| 9 | VDD_DIG1 | power_out | Internal digital core voltage rail (VDD_DIG1); an internal node generated on the chip, not an external supply input. |+| 10 | VIN_IO1 | power_in | Digital I/O supply input tied to VBAT; VIO and VBAT must be tied together at all times, with 2.1 to 3.6 V (direct battery) or 1.76 to 1.9 V (preregulated 1.85 V) recommended. |+| 11 | FLASH_SPI_CLK | output | Fixed-function clock output to the external SPI serial flash; TI recommends enabling internal weak pulldowns during LPDS to minimize flash leakage. |+| 12 | FLASH_SPI_DOUT | output | Fixed-function data output to the external SPI serial flash. |+| 13 | FLASH_SPI_DIN | input | Fixed-function data input from the external SPI serial flash. |+| 14 | FLASH_SPI_CS | output | Fixed-function chip-select output to the external SPI serial flash. |+| 15 | GPIO22 | bidirectional | Multiplexed GPIO22 digital I/O (alternates include McAFSX, GT_CCP04); non-fail-safe, with 2/4/6 mA configurable drive. |+| 16 | TDI | bidirectional | JTAG TDI input in the default pinout after reset, also multiplexed as GPIO23 or UART1_TX; non-fail-safe digital I/O. |+| 17 | TDO | bidirectional | JTAG TDO output in the default pinout after reset, also multiplexed as GPIO24 or PWM0; non-fail-safe digital I/O. |+| 18 | GPIO28 | bidirectional | General-purpose I/O GPIO28 (also GT_PWM03 and the TCK alternate function); non-fail-safe digital I/O. |+| 19 | JTAG/SWD TCK | bidirectional | JTAG/SWD clock input in the default pinout after reset, also multiplexed as GPIO28 or GT_PWM03; non-fail-safe digital I/O. |+| 20 | TMS | bidirectional | JTAG/SWD TMS input in the default pinout after reset, also multiplexed as GPIO29; non-fail-safe digital I/O. |+| 21 | GPIO25 / SOP2 / TCXO_EN | output | Output-only pin used as SOP[2] sense-on-power (2.7 kΩ pull recommended) and as optional external TCXO enable; TI recommends output-only use to avoid spurious SOP sensing. |+| 22 | WLAN_XTAL_N | passive | Negative terminal of the 40-MHz crystal; connect to GND when an external 40-MHz TCXO/XO is used on pin 23. |+| 23 | WLAN_XTAL_P | passive | Positive terminal of the 40-MHz crystal, or the external TCXO/XO clock input (40.00 MHz, 0.7 to 1.2 Vpp sine or clipped sine, AC coupled). |+| 24 | VDD_PLL | power_out | Internal analog voltage rail (VDD_PLL); an internal node, not an external supply input. |+| 25 | LDO_IN2 | power_in | Supply input to the analog RF LDO 2, fed from the ANA DC-DC output. |+| 26 | NC | unconnected | Reserved WLAN analog pin; must be left as no connect. |+| 27 | NC | unconnected | Reserved WLAN analog pin; must be left as no connect. |+| 28 | NC | unconnected | Reserved WLAN analog pin; must be left as no connect. |+| 29 | ANTSEL1 | output | WLAN antenna-select control output for an external RF switch; reserved for this function, not recommended for other use, with 4 mA maximum effective drive. |+| 30 | ANTSEL2 | output | WLAN antenna-select control output for an external RF switch; reserved for this function, not recommended for other use, with 4 mA maximum effective drive. |+| 31 | RF_BG | passive | RF pin for the 2.4-GHz (BG band) WLAN radio; RF pins are rated -0.5 to 2.1 V. |+| 32 | nRESET | input | Active-low master chip reset; must be held low until the VBAT supply is driven and stable, with a simple RC (100 kΩ || 0.1 µF, RC ≈ 10 ms) recommended during power-up. |+| 33 | VDD_PA_IN | power_out | Internal PA supply voltage from the PA DC-DC output; an internal rail, not an external supply input. |+| 34 | SOP1 | input | Sense-on-power input sampled at power-up to select the boot mode; a 100 kΩ pull resistor is recommended and the pin is not available for other functions. |+| 35 | SOP0 | input | Sense-on-power input sampled at power-up to select the boot mode; a 100 kΩ pull resistor is recommended and the pin is not available for other functions. |+| 36 | LDO_IN1 | power_in | Supply input to the analog RF LDO 1, fed from the ANA DC-DC output. |+| 37 | VIN_DCDC_ANA | power_in | Analog DC-DC input connected to the chip input supply VBAT; 2.1 to 3.6 V recommended, absolute maximum 3.8 V. |+| 38 | DCDC_ANA_SW | output | Switching node of the analog DC-DC converter. |+| 39 | VIN_DCDC_PA | power_in | PA DC-DC input connected to the chip input supply VBAT; 2.1 to 3.6 V in wide-voltage mode. |+| 40 | DCDC_PA_SW_P | output | Positive switching node of the PA DC-DC converter. |+| 41 | DCDC_PA_SW_N | output | Negative switching node of the PA DC-DC converter. |+| 42 | DCDC_PA_OUT | power_out | Output of the PA buck converter. |+| 43 | DCDC_DIG_SW | output | Switching node of the digital DC-DC converter. |+| 44 | VIN_DCDC_DIG | power_in | Digital DC-DC input connected to the chip input supply VBAT; 2.1 to 3.6 V in wide-voltage mode or 1.85 V preregulated. |+| 45 | DCDC_ANA2_SW_P / GPIO31 | bidirectional | ANA2 DC-DC positive switching node or GPIO31 digital I/O (alternates include UART0_RX, UART1_RX, McAXR0, GSPI_CLK); for digital use, pin 47 must be shorted to the supply input on CC3200R devices. |+| 46 | DCDC_ANA2_SW_N | output | Negative switching node of the ANA2 DC-DC converter. |+| 47 | VDD_ANA2 | power_out | ANA2 DC-DC output; must be shorted to the supply input rail on CC3200R devices, otherwise the pin is driven by the ANA2 DC-DC. |+| 48 | VDD_ANA1 | power_out | Analog supply rail fed by the ANA2 DC-DC output. |+| 49 | VDD_RAM | power_out | Output of the internal SRAM LDO. |+| 50 | GPIO0 | bidirectional | Multiplexed GPIO0 generic digital I/O (alternates include UART0_CTS, UART1_RTS, UART0_RTS, McAXR0, GSPI_CS), with 4 mA maximum effective drive. |+| 51 | RTC_XTAL_P | passive | Positive terminal of the 32.768-kHz RTC crystal (±150 ppm), or input for an external CMOS-level RTC clock. |+| 52 | RTC_XTAL_N / GPIO32 | passive | Negative terminal of the 32.768-kHz RTC crystal; when used as GPIO32 it is output-only and needs an external 100 kΩ pull-up to the supply rail. |+| 53 | GPIO30 | bidirectional | Multiplexed GPIO30 generic digital I/O (alternates include McACLK, McAFSX, GSPI_MISO, UART0_TX, GT_CCP05), with 4 mA maximum effective drive. |+| 54 | VIN_IO2 | power_in | Digital I/O supply input tied to VBAT; VIO and VBAT must be tied together at all times. |+| 55 | GPIO1 | bidirectional | Multiplexed GPIO1 digital I/O (alternates include pCLK/PIXCLK, UART0_TX, UART1_TX, GT_CCP01); non-fail-safe. |+| 56 | VDD_DIG2 | power_out | Internal digital core voltage rail (VDD_DIG2); an internal node, not an external supply input. |+| 57 | GPIO2 / ADC_CH0 | bidirectional | Shared ADC channel 0 analog input and digital I/O; ADC inputs are tolerant only to 1.8 V, so the digital output must be set Hi-Z before the ADC switch (off by default) is enabled. |+| 58 | GPIO3 / ADC_CH1 | bidirectional | Shared ADC channel 1 analog input and digital I/O; ADC inputs are tolerant only to 1.8 V, so the digital output must be set Hi-Z before the ADC switch (off by default) is enabled. |+| 59 | GPIO4 / ADC_CH2 | bidirectional | Shared ADC channel 2 analog input and digital I/O; ADC inputs are tolerant only to 1.8 V, so the digital output must be set Hi-Z before the ADC switch (off by default) is enabled. |+| 60 | GPIO5 / ADC_CH3 | bidirectional | Shared ADC channel 3 analog input and digital I/O; ADC inputs are tolerant only to 1.8 V, so the digital output must be set Hi-Z before the ADC switch (off by default) is enabled. |+| 61 | GPIO6 | bidirectional | Multiplexed GPIO6 digital I/O (alternates include pDATA4/CAM_D0, UART0_RTS, UART0_CTS, UART1_CTS); non-fail-safe. |+| 62 | GPIO7 | bidirectional | Multiplexed GPIO7 digital I/O (alternates include McACLKX, UART1_RTS, UART0_RTS, UART0_TX); non-fail-safe. |+| 63 | GPIO8 | bidirectional | Multiplexed GPIO8 digital I/O (alternates include SDCARD_IRQ, McAFSX, GT_CCP06); non-fail-safe. |+| 64 | GPIO9 | bidirectional | Multiplexed GPIO9 digital I/O (alternates include SDCARD_DATA, McAXR0, GT_PWM05, GT_CCP00); non-fail-safe. |+| 65 | GND_TAB | power_in | Thermal pad and electrical ground for the device. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-64-EP(9x9) |+| Category | RF And Wireless |+| Pins | 65 |++## CAD (KiCad official)++- Symbol: `CC3200R1M2RGC`+- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`+- 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)+- 3D model files: `cc3200r1m2rgc-etched.step` / `cc3200r1m2rgc-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cc3200r1m2rgc.step` / `cc3200r1m2rgc.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cc3200) (72 pp, sha256 `0376162748d5b86d`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cc3200r1m2rgc-datasheet.pdf)
page.jsonadded+543@@ -0,0 +1,543 @@+{+ "slug": "cc3200r1m2rgc",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments RF Transceiver ICs, VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "rf and wireless",+ "cc3200r1m2rgc",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cc3200r1m2rgc.kicad_sym",+ "cc3200r1m2rgc.kicad_mod",+ "cc3200r1m2rgc.glb",+ "cc3200r1m2rgc.step",+ "cc3200r1m2rgc.lbr",+ "docs/hero.png",+ "docs/cc3200r1m2rgc-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cc3200r1m2rgc-hero.glb",+ "cc3200r1m2rgc-hero.overlay.json"+ ],+ "component": {+ "mpn": "CC3200R1M2RGC",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-64-EP(9x9)",+ "pin_count": 65,+ "category": "RF And Wireless",+ "subcategory": "RF Transceiver ICs",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cc3200",+ "parts": {+ "symbol": "cc3200r1m2rgc.kicad_sym",+ "footprint": "cc3200r1m2rgc.kicad_mod",+ "model_3d": "cc3200r1m2rgc-hero.glb",+ "model_3d_plain": "cc3200r1m2rgc.glb",+ "model_3d_step": "cc3200r1m2rgc-etched.step",+ "model_3d_step_plain": "cc3200r1m2rgc.step",+ "lbr": "cc3200r1m2rgc.lbr"+ },+ "distributor_links": {+ "lcsc": "C1526162",+ "digikey": "296-38012-ND",+ "mouser": "595-CC3200R1M2RGC"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T20:48:49Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-38012-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-CC3200R1M2RGC",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GPIO10",+ "type": "bidirectional",+ "description": "Multiplexed GPIO10 digital I/O (alternates include UART1_TX, SDCARD_CLK, GT_PWM06); non-fail-safe, with 2/4/6 mA configurable drive and 10 µA pull options."+ },+ {+ "number": "2",+ "name": "GPIO11",+ "type": "bidirectional",+ "description": "Multiplexed GPIO11 digital I/O (alternates include pXCLK/XVCLK, SDCARD_CMD, UART1_RX, McAFSX); non-fail-safe, with 2/4/6 mA configurable drive."+ },+ {+ "number": "3",+ "name": "GPIO12",+ "type": "bidirectional",+ "description": "Multiplexed GPIO12 digital I/O (alternates include pVS/VSYNC, I2C_SCL, UART0_TX, GT_CCP03); non-fail-safe, with 2/4/6 mA configurable drive."+ },+ {+ "number": "4",+ "name": "GPIO13",+ "type": "bidirectional",+ "description": "Multiplexed GPIO13 digital I/O (alternates include pHS/HSYNC, I2C_SDA, UART0_RX, GT_CCP04); non-fail-safe, with 2/4/6 mA configurable drive."+ },+ {+ "number": "5",+ "name": "GPIO14",+ "type": "bidirectional",+ "description": "Multiplexed GPIO14 digital I/O (alternates include GSPI_CLK, pDATA8/CAM_D4, I2C_SCL, GT_CCP05); non-fail-safe, with 2/4/6 mA configurable drive."+ },+ {+ "number": "6",+ "name": "GPIO15",+ "type": "bidirectional",+ "description": "Multiplexed GPIO15 digital I/O (alternates include GSPI_MISO, pDATA9/CAM_D5, I2C_SDA, GT_CCP06); non-fail-safe, with 2/4/6 mA configurable drive."+ },+ {+ "number": "7",+ "name": "GPIO16",+ "type": "bidirectional",+ "description": "Multiplexed GPIO16 digital I/O (alternates include GSPI_MOSI, pDATA10/CAM_D6, UART1_TX, GT_CCP07); non-fail-safe, with 2/4/6 mA configurable drive."+ },+ {+ "number": "8",+ "name": "GPIO17",+ "type": "bidirectional",+ "description": "Multiplexed GPIO17 digital I/O (alternates include GSPI_CS, pDATA11/CAM_D7, UART1_RX); non-fail-safe, with 2/4/6 mA configurable drive."+ },+ {+ "number": "9",+ "name": "VDD_DIG1",+ "type": "power_out",+ "description": "Internal digital core voltage rail (VDD_DIG1); an internal node generated on the chip, not an external supply input."+ },+ {+ "number": "10",+ "name": "VIN_IO1",+ "type": "power_in",+ "description": "Digital I/O supply input tied to VBAT; VIO and VBAT must be tied together at all times, with 2.1 to 3.6 V (direct battery) or 1.76 to 1.9 V (preregulated 1.85 V) recommended."+ },+ {+ "number": "11",+ "name": "FLASH_SPI_CLK",+ "type": "output",+ "description": "Fixed-function clock output to the external SPI serial flash; TI recommends enabling internal weak pulldowns during LPDS to minimize flash leakage."+ },+ {+ "number": "12",+ "name": "FLASH_SPI_DOUT",+ "type": "output",+ "description": "Fixed-function data output to the external SPI serial flash."+ },+ {+ "number": "13",+ "name": "FLASH_SPI_DIN",+ "type": "input",+ "description": "Fixed-function data input from the external SPI serial flash."+ },+ {+ "number": "14",+ "name": "FLASH_SPI_CS",+ "type": "output",+ "description": "Fixed-function chip-select output to the external SPI serial flash."+ },+ {+ "number": "15",+ "name": "GPIO22",+ "type": "bidirectional",+ "description": "Multiplexed GPIO22 digital I/O (alternates include McAFSX, GT_CCP04); non-fail-safe, with 2/4/6 mA configurable drive."+ },+ {+ "number": "16",+ "name": "TDI",+ "type": "bidirectional",+ "description": "JTAG TDI input in the default pinout after reset, also multiplexed as GPIO23 or UART1_TX; non-fail-safe digital I/O."+ },+ {+ "number": "17",+ "name": "TDO",+ "type": "bidirectional",+ "description": "JTAG TDO output in the default pinout after reset, also multiplexed as GPIO24 or PWM0; non-fail-safe digital I/O."+ },+ {+ "number": "18",+ "name": "GPIO28",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO28 (also GT_PWM03 and the TCK alternate function); non-fail-safe digital I/O."+ },+ {+ "number": "19",+ "name": "JTAG/SWD TCK",+ "type": "bidirectional",+ "description": "JTAG/SWD clock input in the default pinout after reset, also multiplexed as GPIO28 or GT_PWM03; non-fail-safe digital I/O."+ },+ {+ "number": "20",+ "name": "TMS",+ "type": "bidirectional",+ "description": "JTAG/SWD TMS input in the default pinout after reset, also multiplexed as GPIO29; non-fail-safe digital I/O."+ },+ {+ "number": "21",+ "name": "GPIO25 / SOP2 / TCXO_EN",+ "type": "output",+ "description": "Output-only pin used as SOP[2] sense-on-power (2.7 kΩ pull recommended) and as optional external TCXO enable; TI recommends output-only use to avoid spurious SOP sensing."+ },+ {+ "number": "22",+ "name": "WLAN_XTAL_N",+ "type": "passive",+ "description": "Negative terminal of the 40-MHz crystal; connect to GND when an external 40-MHz TCXO/XO is used on pin 23."+ },+ {+ "number": "23",+ "name": "WLAN_XTAL_P",+ "type": "passive",+ "description": "Positive terminal of the 40-MHz crystal, or the external TCXO/XO clock input (40.00 MHz, 0.7 to 1.2 Vpp sine or clipped sine, AC coupled)."+ },+ {+ "number": "24",+ "name": "VDD_PLL",+ "type": "power_out",+ "description": "Internal analog voltage rail (VDD_PLL); an internal node, not an external supply input."+ },+ {+ "number": "25",+ "name": "LDO_IN2",+ "type": "power_in",+ "description": "Supply input to the analog RF LDO 2, fed from the ANA DC-DC output."+ },+ {+ "number": "26",+ "name": "NC",+ "type": "unconnected",+ "description": "Reserved WLAN analog pin; must be left as no connect."+ },+ {+ "number": "27",+ "name": "NC",+ "type": "unconnected",+ "description": "Reserved WLAN analog pin; must be left as no connect."+ },+ {+ "number": "28",+ "name": "NC",+ "type": "unconnected",+ "description": "Reserved WLAN analog pin; must be left as no connect."+ },+ {+ "number": "29",+ "name": "ANTSEL1",+ "type": "output",+ "description": "WLAN antenna-select control output for an external RF switch; reserved for this function, not recommended for other use, with 4 mA maximum effective drive."+ },+ {+ "number": "30",+ "name": "ANTSEL2",+ "type": "output",+ "description": "WLAN antenna-select control output for an external RF switch; reserved for this function, not recommended for other use, with 4 mA maximum effective drive."+ },+ {+ "number": "31",+ "name": "RF_BG",+ "type": "passive",+ "description": "RF pin for the 2.4-GHz (BG band) WLAN radio; RF pins are rated -0.5 to 2.1 V."+ },+ {+ "number": "32",+ "name": "nRESET",+ "type": "input",+ "description": "Active-low master chip reset; must be held low until the VBAT supply is driven and stable, with a simple RC (100 kΩ || 0.1 µF, RC ≈ 10 ms) recommended during power-up."+ },+ {+ "number": "33",+ "name": "VDD_PA_IN",+ "type": "power_out",+ "description": "Internal PA supply voltage from the PA DC-DC output; an internal rail, not an external supply input."+ },+ {+ "number": "34",+ "name": "SOP1",+ "type": "input",+ "description": "Sense-on-power input sampled at power-up to select the boot mode; a 100 kΩ pull resistor is recommended and the pin is not available for other functions."+ },+ {+ "number": "35",+ "name": "SOP0",+ "type": "input",+ "description": "Sense-on-power input sampled at power-up to select the boot mode; a 100 kΩ pull resistor is recommended and the pin is not available for other functions."+ },+ {+ "number": "36",+ "name": "LDO_IN1",+ "type": "power_in",+ "description": "Supply input to the analog RF LDO 1, fed from the ANA DC-DC output."+ },+ {+ "number": "37",+ "name": "VIN_DCDC_ANA",+ "type": "power_in",+ "description": "Analog DC-DC input connected to the chip input supply VBAT; 2.1 to 3.6 V recommended, absolute maximum 3.8 V."+ },+ {+ "number": "38",+ "name": "DCDC_ANA_SW",+ "type": "output",+ "description": "Switching node of the analog DC-DC converter."+ },+ {+ "number": "39",+ "name": "VIN_DCDC_PA",+ "type": "power_in",+ "description": "PA DC-DC input connected to the chip input supply VBAT; 2.1 to 3.6 V in wide-voltage mode."+ },+ {+ "number": "40",+ "name": "DCDC_PA_SW_P",+ "type": "output",+ "description": "Positive switching node of the PA DC-DC converter."+ },+ {+ "number": "41",+ "name": "DCDC_PA_SW_N",+ "type": "output",+ "description": "Negative switching node of the PA DC-DC converter."+ },+ {+ "number": "42",+ "name": "DCDC_PA_OUT",+ "type": "power_out",+ "description": "Output of the PA buck converter."+ },+ {+ "number": "43",+ "name": "DCDC_DIG_SW",+ "type": "output",+ "description": "Switching node of the digital DC-DC converter."+ },+ {+ "number": "44",+ "name": "VIN_DCDC_DIG",+ "type": "power_in",+ "description": "Digital DC-DC input connected to the chip input supply VBAT; 2.1 to 3.6 V in wide-voltage mode or 1.85 V preregulated."+ },+ {+ "number": "45",+ "name": "DCDC_ANA2_SW_P / GPIO31",+ "type": "bidirectional",+ "description": "ANA2 DC-DC positive switching node or GPIO31 digital I/O (alternates include UART0_RX, UART1_RX, McAXR0, GSPI_CLK); for digital use, pin 47 must be shorted to the supply input on CC3200R devices."+ },+ {+ "number": "46",+ "name": "DCDC_ANA2_SW_N",+ "type": "output",+ "description": "Negative switching node of the ANA2 DC-DC converter."+ },+ {+ "number": "47",+ "name": "VDD_ANA2",+ "type": "power_out",+ "description": "ANA2 DC-DC output; must be shorted to the supply input rail on CC3200R devices, otherwise the pin is driven by the ANA2 DC-DC."+ },+ {+ "number": "48",+ "name": "VDD_ANA1",+ "type": "power_out",+ "description": "Analog supply rail fed by the ANA2 DC-DC output."+ },+ {+ "number": "49",+ "name": "VDD_RAM",+ "type": "power_out",+ "description": "Output of the internal SRAM LDO."+ },+ {+ "number": "50",+ "name": "GPIO0",+ "type": "bidirectional",+ "description": "Multiplexed GPIO0 generic digital I/O (alternates include UART0_CTS, UART1_RTS, UART0_RTS, McAXR0, GSPI_CS), with 4 mA maximum effective drive."+ },+ {+ "number": "51",+ "name": "RTC_XTAL_P",+ "type": "passive",+ "description": "Positive terminal of the 32.768-kHz RTC crystal (±150 ppm), or input for an external CMOS-level RTC clock."+ },+ {+ "number": "52",+ "name": "RTC_XTAL_N / GPIO32",+ "type": "passive",+ "description": "Negative terminal of the 32.768-kHz RTC crystal; when used as GPIO32 it is output-only and needs an external 100 kΩ pull-up to the supply rail."+ },+ {+ "number": "53",+ "name": "GPIO30",+ "type": "bidirectional",+ "description": "Multiplexed GPIO30 generic digital I/O (alternates include McACLK, McAFSX, GSPI_MISO, UART0_TX, GT_CCP05), with 4 mA maximum effective drive."+ },+ {+ "number": "54",+ "name": "VIN_IO2",+ "type": "power_in",+ "description": "Digital I/O supply input tied to VBAT; VIO and VBAT must be tied together at all times."+ },+ {+ "number": "55",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "Multiplexed GPIO1 digital I/O (alternates include pCLK/PIXCLK, UART0_TX, UART1_TX, GT_CCP01); non-fail-safe."+ },+ {+ "number": "56",+ "name": "VDD_DIG2",+ "type": "power_out",+ "description": "Internal digital core voltage rail (VDD_DIG2); an internal node, not an external supply input."+ },+ {+ "number": "57",+ "name": "GPIO2 / ADC_CH0",+ "type": "bidirectional",+ "description": "Shared ADC channel 0 analog input and digital I/O; ADC inputs are tolerant only to 1.8 V, so the digital output must be set Hi-Z before the ADC switch (off by default) is enabled."+ },+ {+ "number": "58",+ "name": "GPIO3 / ADC_CH1",+ "type": "bidirectional",+ "description": "Shared ADC channel 1 analog input and digital I/O; ADC inputs are tolerant only to 1.8 V, so the digital output must be set Hi-Z before the ADC switch (off by default) is enabled."+ },+ {+ "number": "59",+ "name": "GPIO4 / ADC_CH2",+ "type": "bidirectional",+ "description": "Shared ADC channel 2 analog input and digital I/O; ADC inputs are tolerant only to 1.8 V, so the digital output must be set Hi-Z before the ADC switch (off by default) is enabled."+ },+ {+ "number": "60",+ "name": "GPIO5 / ADC_CH3",+ "type": "bidirectional",+ "description": "Shared ADC channel 3 analog input and digital I/O; ADC inputs are tolerant only to 1.8 V, so the digital output must be set Hi-Z before the ADC switch (off by default) is enabled."+ },+ {+ "number": "61",+ "name": "GPIO6",+ "type": "bidirectional",+ "description": "Multiplexed GPIO6 digital I/O (alternates include pDATA4/CAM_D0, UART0_RTS, UART0_CTS, UART1_CTS); non-fail-safe."+ },+ {+ "number": "62",+ "name": "GPIO7",+ "type": "bidirectional",+ "description": "Multiplexed GPIO7 digital I/O (alternates include McACLKX, UART1_RTS, UART0_RTS, UART0_TX); non-fail-safe."+ },+ {+ "number": "63",+ "name": "GPIO8",+ "type": "bidirectional",+ "description": "Multiplexed GPIO8 digital I/O (alternates include SDCARD_IRQ, McAFSX, GT_CCP06); non-fail-safe."+ },+ {+ "number": "64",+ "name": "GPIO9",+ "type": "bidirectional",+ "description": "Multiplexed GPIO9 digital I/O (alternates include SDCARD_DATA, McAXR0, GT_PWM05, GT_CCP00); non-fail-safe."+ },+ {+ "number": "65",+ "name": "GND_TAB",+ "type": "power_in",+ "description": "Thermal pad and electrical ground for the device."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet gives no KiCad electrical type for internal supply/regulator nodes. I typed them power; Pins are multiplexed (GPIO, JTAG/SWD, ADC, camera, SPI-flash). I typed each as bidirectional because; Pins 51 and 52 are 32.768-kHz RTC crystal pins, and 22 and 23 are 40-MHz crystal/TCXO pins. I typed ",+ "13/65 pins cited to the wrong page (name found elsewhere): ['11:FLASH_SPI_CLK@p10', '12:FLASH_SPI_DOUT@p11', '13:FLASH_SPI_DIN@p11', '14:FLASH_SPI_CS@p11']"+ ],+ "pages_sent": 72,+ "cost_usd": 0.157,+ "at": "2026-10-08T20:48:11"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cc3200",+ "pages": 72,+ "sha256": "0376162748d5b86d",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 65,+ "described": 65,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cc3200r1m2rgc.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "dce07a86ec3fe3ca87eebdff13827f55e036ced5518fee01f85cec4a3f56366d",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cc3200r1m2rgc-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "5dcc349454a96283a891134eb88bf084634dd7c895b8f92895abb8209243deca",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}