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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

CC3200R1M2RGC

Texas Instruments · RF Transceiver ICs · VQFN-64-EP(9x9)

CC3200R1M2RGC from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GPIO10	bidirectional	Multiplexed GPIO10 digital I/O (alternates include UART1_TX, SDCARD_CLK, GT_PWM06); non-fail-safe, with 2/4/6 mA configurable drive and 10 µA pull options.
2	GPIO11	bidirectional	Multiplexed GPIO11 digital I/O (alternates include pXCLK/XVCLK, SDCARD_CMD, UART1_RX, McAFSX); non-fail-safe, with 2/4/6 mA configurable drive.
3	GPIO12	bidirectional	Multiplexed GPIO12 digital I/O (alternates include pVS/VSYNC, I2C_SCL, UART0_TX, GT_CCP03); non-fail-safe, with 2/4/6 mA configurable drive.
4	GPIO13	bidirectional	Multiplexed GPIO13 digital I/O (alternates include pHS/HSYNC, I2C_SDA, UART0_RX, GT_CCP04); non-fail-safe, with 2/4/6 mA configurable drive.
5	GPIO14	bidirectional	Multiplexed GPIO14 digital I/O (alternates include GSPI_CLK, pDATA8/CAM_D4, I2C_SCL, GT_CCP05); non-fail-safe, with 2/4/6 mA configurable drive.
6	GPIO15	bidirectional	Multiplexed GPIO15 digital I/O (alternates include GSPI_MISO, pDATA9/CAM_D5, I2C_SDA, GT_CCP06); non-fail-safe, with 2/4/6 mA configurable drive.
7	GPIO16	bidirectional	Multiplexed GPIO16 digital I/O (alternates include GSPI_MOSI, pDATA10/CAM_D6, UART1_TX, GT_CCP07); non-fail-safe, with 2/4/6 mA configurable drive.
8	GPIO17	bidirectional	Multiplexed GPIO17 digital I/O (alternates include GSPI_CS, pDATA11/CAM_D7, UART1_RX); non-fail-safe, with 2/4/6 mA configurable drive.
9	VDD_DIG1	power_out	Internal digital core voltage rail (VDD_DIG1); an internal node generated on the chip, not an external supply input.
10	VIN_IO1	power_in	Digital I/O supply input tied to VBAT; VIO and VBAT must be tied together at all times, with 2.1 to 3.6 V (direct battery) or 1.76 to 1.9 V (preregulated 1.85 V) recommended.
11	FLASH_SPI_CLK	output	Fixed-function clock output to the external SPI serial flash; TI recommends enabling internal weak pulldowns during LPDS to minimize flash leakage.
12	FLASH_SPI_DOUT	output	Fixed-function data output to the external SPI serial flash.
13	FLASH_SPI_DIN	input	Fixed-function data input from the external SPI serial flash.
14	FLASH_SPI_CS	output	Fixed-function chip-select output to the external SPI serial flash.
15	GPIO22	bidirectional	Multiplexed GPIO22 digital I/O (alternates include McAFSX, GT_CCP04); non-fail-safe, with 2/4/6 mA configurable drive.
16	TDI	bidirectional	JTAG TDI input in the default pinout after reset, also multiplexed as GPIO23 or UART1_TX; non-fail-safe digital I/O.
17	TDO	bidirectional	JTAG TDO output in the default pinout after reset, also multiplexed as GPIO24 or PWM0; non-fail-safe digital I/O.
18	GPIO28	bidirectional	General-purpose I/O GPIO28 (also GT_PWM03 and the TCK alternate function); non-fail-safe digital I/O.
19	JTAG/SWD TCK	bidirectional	JTAG/SWD clock input in the default pinout after reset, also multiplexed as GPIO28 or GT_PWM03; non-fail-safe digital I/O.
20	TMS	bidirectional	JTAG/SWD TMS input in the default pinout after reset, also multiplexed as GPIO29; non-fail-safe digital I/O.
21	GPIO25 / SOP2 / TCXO_EN	output	Output-only pin used as SOP[2] sense-on-power (2.7 kΩ pull recommended) and as optional external TCXO enable; TI recommends output-only use to avoid spurious SOP sensing.
22	WLAN_XTAL_N	passive	Negative terminal of the 40-MHz crystal; connect to GND when an external 40-MHz TCXO/XO is used on pin 23.
23	WLAN_XTAL_P	passive	Positive terminal of the 40-MHz crystal, or the external TCXO/XO clock input (40.00 MHz, 0.7 to 1.2 Vpp sine or clipped sine, AC coupled).
24	VDD_PLL	power_out	Internal analog voltage rail (VDD_PLL); an internal node, not an external supply input.
25	LDO_IN2	power_in	Supply input to the analog RF LDO 2, fed from the ANA DC-DC output.
26	NC	unconnected	Reserved WLAN analog pin; must be left as no connect.
27	NC	unconnected	Reserved WLAN analog pin; must be left as no connect.
28	NC	unconnected	Reserved WLAN analog pin; must be left as no connect.
29	ANTSEL1	output	WLAN antenna-select control output for an external RF switch; reserved for this function, not recommended for other use, with 4 mA maximum effective drive.
30	ANTSEL2	output	WLAN antenna-select control output for an external RF switch; reserved for this function, not recommended for other use, with 4 mA maximum effective drive.
31	RF_BG	passive	RF pin for the 2.4-GHz (BG band) WLAN radio; RF pins are rated -0.5 to 2.1 V.
32	nRESET	input	Active-low master chip reset; must be held low until the VBAT supply is driven and stable, with a simple RC (100 kΩ
33	VDD_PA_IN	power_out	Internal PA supply voltage from the PA DC-DC output; an internal rail, not an external supply input.
34	SOP1	input	Sense-on-power input sampled at power-up to select the boot mode; a 100 kΩ pull resistor is recommended and the pin is not available for other functions.
35	SOP0	input	Sense-on-power input sampled at power-up to select the boot mode; a 100 kΩ pull resistor is recommended and the pin is not available for other functions.
36	LDO_IN1	power_in	Supply input to the analog RF LDO 1, fed from the ANA DC-DC output.
37	VIN_DCDC_ANA	power_in	Analog DC-DC input connected to the chip input supply VBAT; 2.1 to 3.6 V recommended, absolute maximum 3.8 V.
38	DCDC_ANA_SW	output	Switching node of the analog DC-DC converter.
39	VIN_DCDC_PA	power_in	PA DC-DC input connected to the chip input supply VBAT; 2.1 to 3.6 V in wide-voltage mode.
40	DCDC_PA_SW_P	output	Positive switching node of the PA DC-DC converter.
41	DCDC_PA_SW_N	output	Negative switching node of the PA DC-DC converter.
42	DCDC_PA_OUT	power_out	Output of the PA buck converter.
43	DCDC_DIG_SW	output	Switching node of the digital DC-DC converter.
44	VIN_DCDC_DIG	power_in	Digital DC-DC input connected to the chip input supply VBAT; 2.1 to 3.6 V in wide-voltage mode or 1.85 V preregulated.
45	DCDC_ANA2_SW_P / GPIO31	bidirectional	ANA2 DC-DC positive switching node or GPIO31 digital I/O (alternates include UART0_RX, UART1_RX, McAXR0, GSPI_CLK); for digital use, pin 47 must be shorted to the supply input on CC3200R devices.
46	DCDC_ANA2_SW_N	output	Negative switching node of the ANA2 DC-DC converter.
47	VDD_ANA2	power_out	ANA2 DC-DC output; must be shorted to the supply input rail on CC3200R devices, otherwise the pin is driven by the ANA2 DC-DC.
48	VDD_ANA1	power_out	Analog supply rail fed by the ANA2 DC-DC output.
49	VDD_RAM	power_out	Output of the internal SRAM LDO.
50	GPIO0	bidirectional	Multiplexed GPIO0 generic digital I/O (alternates include UART0_CTS, UART1_RTS, UART0_RTS, McAXR0, GSPI_CS), with 4 mA maximum effective drive.
51	RTC_XTAL_P	passive	Positive terminal of the 32.768-kHz RTC crystal (±150 ppm), or input for an external CMOS-level RTC clock.
52	RTC_XTAL_N / GPIO32	passive	Negative terminal of the 32.768-kHz RTC crystal; when used as GPIO32 it is output-only and needs an external 100 kΩ pull-up to the supply rail.
53	GPIO30	bidirectional	Multiplexed GPIO30 generic digital I/O (alternates include McACLK, McAFSX, GSPI_MISO, UART0_TX, GT_CCP05), with 4 mA maximum effective drive.
54	VIN_IO2	power_in	Digital I/O supply input tied to VBAT; VIO and VBAT must be tied together at all times.
55	GPIO1	bidirectional	Multiplexed GPIO1 digital I/O (alternates include pCLK/PIXCLK, UART0_TX, UART1_TX, GT_CCP01); non-fail-safe.
56	VDD_DIG2	power_out	Internal digital core voltage rail (VDD_DIG2); an internal node, not an external supply input.
57	GPIO2 / ADC_CH0	bidirectional	Shared ADC channel 0 analog input and digital I/O; ADC inputs are tolerant only to 1.8 V, so the digital output must be set Hi-Z before the ADC switch (off by default) is enabled.
58	GPIO3 / ADC_CH1	bidirectional	Shared ADC channel 1 analog input and digital I/O; ADC inputs are tolerant only to 1.8 V, so the digital output must be set Hi-Z before the ADC switch (off by default) is enabled.
59	GPIO4 / ADC_CH2	bidirectional	Shared ADC channel 2 analog input and digital I/O; ADC inputs are tolerant only to 1.8 V, so the digital output must be set Hi-Z before the ADC switch (off by default) is enabled.
60	GPIO5 / ADC_CH3	bidirectional	Shared ADC channel 3 analog input and digital I/O; ADC inputs are tolerant only to 1.8 V, so the digital output must be set Hi-Z before the ADC switch (off by default) is enabled.
61	GPIO6	bidirectional	Multiplexed GPIO6 digital I/O (alternates include pDATA4/CAM_D0, UART0_RTS, UART0_CTS, UART1_CTS); non-fail-safe.
62	GPIO7	bidirectional	Multiplexed GPIO7 digital I/O (alternates include McACLKX, UART1_RTS, UART0_RTS, UART0_TX); non-fail-safe.
63	GPIO8	bidirectional	Multiplexed GPIO8 digital I/O (alternates include SDCARD_IRQ, McAFSX, GT_CCP06); non-fail-safe.
64	GPIO9	bidirectional	Multiplexed GPIO9 digital I/O (alternates include SDCARD_DATA, McAXR0, GT_PWM05, GT_CCP00); non-fail-safe.
65	GND_TAB	power_in	Thermal pad and electrical ground for the device.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-64-EP(9x9)
Category	RF And Wireless
Pins	65

CAD (KiCad official)

Symbol: CC3200R1M2RGC
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
3D model files: cc3200r1m2rgc-etched.step / cc3200r1m2rgc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cc3200r1m2rgc.step / cc3200r1m2rgc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (72 pp, sha256 0376162748d5b86d, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF