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CC3135RNMRGKR

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Texas Instruments RF Transceiver ICs, VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CC3135RNMRGKR

Texas Instruments · RF Transceiver ICs · VQFN-64-EP(9x9)

CC3135RNMRGKR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIO10 bidirectional Digital input or output, also used for antenna selection, hostless mode and BLE/2.4 GHz coexistence signals.
2 nHIB input Active-low hibernate signal input to the NWP subsystem; add a pullup on the board if the MCU GPIO can float during low-power mode.
3 DIO12 bidirectional Digital input or output, also used for antenna selection, hostless mode and coexistence signals.
4 DIO13 bidirectional Digital input or output, also used for antenna selection, hostless mode and coexistence signals.
5 HOST_SPI_CLK input Host interface SPI clock input from the MCU host, up to 20 MHz.
6 HOST_SPI_MOSI input Host interface SPI data input from the MCU host.
7 HOST_SPI_MISO output Host interface SPI data output to the MCU host.
8 HOST_SPI_nCS input Host interface SPI chip select from the MCU host, active low.
9 VDD_DIG1 power_in Digital core supply, 1.2 V.
10 VIN_IO1 power_in I/O supply, tied to VBAT; recommended supply range 2.1 V to 3.6 V.
11 FLASH_SPI_CLK output Serial flash interface SPI clock to the external flash, up to 20 MHz.
12 FLASH_SPI_MOSI output Serial flash interface SPI data output to the external flash.
13 FLASH_SPI_MISO input Serial flash interface SPI data input from the external flash.
14 FLASH_SPI_CS output Serial flash interface SPI chip select to the external flash, active low.
15 HOST_INTR output Interrupt output to the host, active high.
16 DIO23 bidirectional Digital input or output, also used for antenna selection, hostless mode and coexistence signals.
17 DIO24 bidirectional Digital input or output, also used for antenna selection, hostless mode and coexistence signals.
18 DIO28 bidirectional Digital input or output; LPDS retention is unavailable on this pin.
19 Reserved passive Reserved pin; connect a 100-kΩ pulldown resistor to ground.
20 DIO29 bidirectional Digital input or output, also used for antenna selection, hostless mode and coexistence signals.
21 SOP2/TCXO_EN output Sense-on-power 2 (restore-to-default control) and external TCXO enable; output only, add a 10-kΩ pulldown to ground.
22 WLAN_XTAL_N passive Connect the WLAN 40-MHz crystal here; pull down if an external TCXO is used.
23 WLAN_XTAL_P passive Connect the WLAN 40-MHz crystal here, or the external TCXO clock input.
24 VDD_PLL power_in Internal PLL power supply, 1.4 V nominal.
25 LDO_IN2 power_in Input to the internal LDO.
26 NC unconnected No connect; leave unused.
27 A_RX input WLAN analog 5 GHz A-band RF receive input.
28 A_TX output WLAN analog 5 GHz A-band RF transmit output.
29 GND power_in Ground.
30 GND power_in Ground.
31 RF_BG bidirectional WLAN analog 2.4 GHz RF transmit/receive for the 802.11 b/g bands.
32 nRESET input Active-low global device reset; use an RC circuit (100 kΩ
33 VDD_PA_IN power_in Power supply for the RF power amplifier, from the PA DC/DC output.
34 SOP1 input Sense-on-power 1 used for factory restore and 5 GHz switch control; add a 100-kΩ pulldown to ground.
35 SOP0 input Sense-on-power 0 used for factory restore and 5 GHz switch control; add a 100-kΩ pulldown to ground.
36 LDO_IN1 power_in Input to the internal LDO.
37 VIN_DCDC_ANA power_in Power supply input for the analog DC/DC converter, connected to the device input supply VBAT.
38 DCDC_ANA_SW power_out Analog DC/DC converter switching node output.
39 VIN_DCDC_PA power_in PA DC/DC converter input supply, connected to the device input supply VBAT.
40 DCDC_PA_SW_P power_out PA DC/DC converter positive switching node output.
41 DCDC_PA_SW_N power_out PA DC/DC converter negative switching node output.
42 DCDC_PA_OUT power_out PA DC/DC converter output; connect the DC/DC output capacitor here.
43 DCDC_DIG_SW power_out Digital DC/DC converter switching node output.
44 VIN_DCDC_DIG power_in Power supply input for the digital DC/DC converter, connected to VBAT.
45 DIO31 bidirectional Network Scripter digital I/O; LPDS retention is unavailable on this pin.
46 DCDC_ANA2_SW_N power_out Analog2 DC/DC converter negative switching node output.
47 VDD_ANA2 power_out Analog2 supply node; the datasheet describes it as the internal analog-to-DC/DC output.
48 VDD_ANA1 power_in Analog1 power supply input, fed by the ANA2 DC/DC output.
49 VDD_RAM power_out Internal SRAM LDO output that supplies the internal RAM.
50 UART1_nRTS output UART host interface request-to-send, active low.
51 RTC_XTAL_P passive Connect a 32.768-kHz crystal here, or force an external CMOS-level clock input.
52 RTC_XTAL_N passive Connect a 32.768-kHz crystal here, or a 100-kΩ pullup to supply for external clock; LPDS retention is unavailable.
53 DIO30 bidirectional Network Scripter digital I/O; LPDS retention is unavailable on this pin.
54 VIN_IO2 power_in I/O power supply, same as battery voltage (tie to VBAT).
55 UART1_TX output UART host interface TX; connect to a test point on the prototype for flash programming.
56 VDD_DIG2 power_in Digital power supply, 1.2 V.
57 UART1_RX input UART host interface RX; connect to a test point on the prototype for flash programming.
58 TEST_58 output Test signal; connect to an external test point.
59 TEST_59 output Test signal; connect to an external test point.
60 TEST_60 output Test signal; connect to an external test point.
61 UART1_nCTS input UART host interface clear-to-send, active low.
62 TEST_62 output Test signal; connect to an external test point.
63 DIO8 bidirectional Digital input or output, also used for antenna selection, hostless mode and coexistence signals.
64 DIO9 bidirectional Digital input or output, also used for antenna selection, hostless mode and coexistence signals.
65 GND power_in Ground tab used as the thermal and electrical ground (exposed pad).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category RF & Radio
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (VBAT and VIO pins) -0.5 3.8 V VBAT and VIO pins 37, 39, 44 17
Digital inputs (printed max VIO + 0.5) -0.5 V 17
RF pins -0.5 2.1 V RF pins 17
Analog pins, crystal pins -0.5 2.1 V Pins 22, 23, 51, 52 17
Operating temperature TA -40 85 °C Over operating free-air temperature range 17
Storage temperature Tstg -55 125 °C 17
Electrostatic discharge, human body model (HBM) VESD -2000 2000 V Per ANSI/ESDA/JEDEC JS-001 17
Electrostatic discharge, charged device model (CDM) VESD -500 500 V Per ANSI/ESDA/JEDEC JS-002 17
Supply voltage VBAT, VIO (shorted to VBAT) 2.1 3.3 3.6 V Direct battery connection; pins 10, 37, 39, 44, 54 18
Ambient thermal slew -20 20 °C/minute 18
High-level input current (DIO except 52, 53) IIH 5 nA 23
Low-level input current (DIO except 52, 53) IIL 5 nA 23
High-level source current, 2-mA drive IOH 2 mA 2-mA drive 23
High-level source current, 4-mA drive IOH 4 mA 4-mA drive 23
High-level source current, 6-mA drive IOH 6 mA 6-mA drive 23
Low-level sink current, 2-mA drive IOL 2 mA 2-mA drive 23
Low-level sink current, 4-mA drive IOL 4 mA 4-mA drive 23
Low-level sink current, 6-mA drive IOL 6 mA 6-mA drive 23
High-level input current (DIO 52, 53) IIH 50 nA 24
Low-level input current (DIO 52, 53) IIL 50 nA 24
High-level source current, 2-mA drive (DIO 52, 53) IOH 1.5 mA VOH = 2.4; 2-mA drive 24
High-level source current, 4-mA drive (DIO 52, 53) IOH 2.5 mA VOH = 2.4; 4-mA drive 24
High-level source current, 6-mA drive (DIO 52, 53) IOH 3.5 mA VOH = 2.4; 6-mA drive 24
Low-level sink current, 2-mA drive (DIO 52, 53) IOL 1.5 mA 2-mA drive 24
Low-level sink current, 4-mA drive (DIO 52, 53) IOL 2.5 mA 4-mA drive 24
Low-level sink current, 6-mA drive (DIO 52, 53) IOL 3.5 mA 6-mA drive 24
Low-level input voltage nRESET VIL 0.6 V nRESET 24
Pullup current IOH 5 10 µA VOH = 2.4 (VDD = 3.0 V) 25
Pulldown current IOL 5 µA VOL = 0.4 (VDD = 3.0 V) 25
Operating frequency range, 2.4 GHz 2412 2472 MHz 26
Transmit center frequency accuracy, 2.4 GHz -25 25 ppm 26
Operating frequency range, 5 GHz 5180 5825 MHz 26
Transmit center frequency accuracy, 5 GHz -20 20 ppm 26
nReset time after VBAT and VIO stable (32-kHz crystal) T1 1 ms nReset timing after VBAT and VIO supply are stable 29
Hardware wake-up time (32-kHz crystal) T2 25 ms 29
Initialization time (32-kHz crystal) T3 1.35 s 32-kHz crystal settling plus firmware initialization time plus radio calibration 29
nReset time after VBAT and VIO stable (external 32-kHz) T1 1 ms nReset timing after VBAT and VIO supply are stable 30
Hardware wake-up time (external 32-kHz) T2 25 ms 30
Initialization time (external 32-kHz) T3 250 ms Firmware initialization time plus radio calibration 30
Minimum hibernate time (nHIB low pulse width) Thib_min 10 ms Minimum pulse width of nHIB being low 31
Wakeup time from HIBERNATE (hardware plus firmware init) Twake_from_hib 50 ms Note 2: +200 ms if temperature changes by more than 20°C 31
RTC crystal frequency accuracy -150 150 ppm Initial plus temperature plus aging 32
RTC crystal ESR (32.768 kHz) 70 kΩ 32.768 kHz 32
External RTC frequency accuracy -150 150 ppm Initial plus temperature plus aging 33
External RTC input transition time tr, tf tr, tf 100 ns 10% to 90% 33
External RTC input duty cycle 20 50 80 % 33
Fast clock (Fref) crystal frequency accuracy -20 20 ppm Initial plus temperature plus aging 34
Fast clock (Fref) crystal ESR, 40 MHz 60 Ω 40 MHz 34
External Fref clock frequency accuracy (-40°C to +85°C) -20 20 ppm Initial plus temperature plus aging 35
External Fref clock input duty cycle 45 50 55 % 35
External Fref clock voltage (Vpp) Vpp 0.7 1.2 Vpp Sine or clipped sine wave, AC coupled 35
Clock frequency at VBAT = 3.3 V (Host SPI) F 20 MHz VBAT = 3.3 V; maximum load 20 pF at 3.3 V 36
Clock frequency at VBAT ≤ 2.1 V (Host SPI) F 12 MHz VBAT ≤ 2.1 V; maximum load 20 pF at 3.3 V 36
Clock period (Host SPI) tclk 50 ns Maximum load 20 pF at 3.3 V 36
Clock low period (Host SPI) tLP 25 ns Maximum load 20 pF at 3.3 V 36
Clock high period (Host SPI) tHT 25 ns Maximum load 20 pF at 3.3 V 36
RX data setup time (Host SPI) tIS 4 ns Maximum load 20 pF at 3.3 V 36
RX data hold time (Host SPI) tIH 4 ns Maximum load 20 pF at 3.3 V 36
TX data output delay (Host SPI) tOD 20 ns Maximum load 20 pF at 3.3 V 36
TX data hold time (Host SPI) tOH 24 ns Maximum load 20 pF at 3.3 V 36

CAD (KiCad official)

  • Symbol: CC3135RNMRGKR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: cc3135rnmrgkr-etched.step / cc3135rnmrgkr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cc3135rnmrgkr.step / cc3135rnmrgkr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (84 pp, sha256 100e2d1c10709655, retrieved 2026-10-28, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF