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CC3130RNMRGKR

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Texas Instruments RF Transceiver ICs, VQFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentradio frequency chip-antennacc3130rnmrgkrfactory-2.0.0extractor-text

Verified CC3130RNMRGKR

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CC3130RNMRGKR · VQFN-64(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 76-page datasheet
  • ✓distributor: lcsc C2862147, digikey 296-CC3130RNMRGKRTR-ND, mouser 595-CC3130RNMRGKR
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-aktbgiey/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.73)
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cc3130rnmrgkr.kicad_sym✓ cc3130rnmrgkr.kicad_mod✓ cc3130rnmrgkr.step
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CC3130RNMRGKR

Texas Instruments · RF Transceiver ICs · VQFN-64(9x9)

CC3130RNMRGKR from Texas Instruments, in a VQFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIO10 bidirectional Digital input or output, multiplexed with antenna-select control, hostless-mode I/O and BLE/2.4GHz coexistence I/O.
2 nHIB input Active-low hibernate signal input to the NWP subsystem, driven from an MCU GPIO; add a pullup if that GPIO can float during MCU low-power states.
3 DIO12 bidirectional Digital input or output, multiplexed with antenna-select control, hostless-mode I/O and BLE/2.4GHz coexistence I/O.
4 DIO13 bidirectional Digital input or output, multiplexed with antenna-select control, hostless-mode I/O and BLE/2.4GHz coexistence I/O.
5 HOST_SPI_CLK input Host interface SPI clock input from the MCU host, up to 20MHz.
6 HOST_SPI_MOSI input Host interface SPI data input from the MCU host.
7 HOST_SPI_MISO output Host interface SPI data output to the MCU host.
8 HOST_SPI_nCS input Host interface SPI chip select from the MCU host, active low.
9 VDD_DIG1 power_in Digital core supply rail, 1.2 V.
10 VIN_IO1 power_in I/O supply input, tied to the battery voltage VBAT (recommended 2.1 V to 3.6 V).
11 FLASH_SPI_CLK output Serial flash SPI clock output from the CC3130 to the external flash, up to 20MHz.
12 FLASH_SPI_MOSI output Serial flash SPI data output from the CC3130 to the external flash.
13 FLASH_SPI_MISO input Serial flash SPI data input from the external flash.
14 FLASH_SPI_CS output Serial flash SPI chip select output to the external flash, active low.
15 HOST_INTR output Interrupt output to the host MCU, active high.
16 DIO23 bidirectional Digital input or output, multiplexed with antenna-select control, hostless-mode I/O and BLE/2.4GHz coexistence I/O.
17 DIO24 bidirectional Digital input or output, multiplexed with antenna-select control, hostless-mode I/O and BLE/2.4GHz coexistence I/O.
18 DIO28 bidirectional Digital input or output, multiplexed with hostless-mode and BLE/2.4GHz coexistence functions; LPDS retention is unavailable on this pin.
19 Reserved passive Reserved pin; connect a 100kΩ pulldown resistor to ground.
20 DIO29 bidirectional Digital input or output, multiplexed with antenna-select control, hostless-mode I/O and BLE/2.4GHz coexistence I/O.
21 SOP2/TCXO_EN output Sense-on-power bit 2 for device mode and factory restore, also the external TCXO enable output; must be used as an output only and needs a pulldown to ground.
22 WLAN_XTAL_N passive Connect the WLAN 40MHz crystal here; pull down to ground if an external TCXO is used.
23 WLAN_XTAL_P passive Connect the WLAN 40MHz crystal here, or use as the TCXO clock input.
24 VDD_PLL power_in Internal PLL supply, 1.4 V nominal.
25 LDO_IN2 power_in Input to the internal LDO, fed from the analog DC/DC output.
26 NC unconnected No connect; leave unconnected.
27 NC unconnected No connect; leave unconnected.
28 NC unconnected No connect; leave unconnected.
29 ANTSEL1 output Antenna-select control 1 for an external RF switch; the pin table marks it reserved for future use and it must not be used for other functions.
30 ANTSEL2 output Antenna-select control 2 for an external RF switch; the pin table marks it reserved for future use and it must not be used for other functions.
31 RF_BG passive 2.4GHz RF transmit/receive pin for the 802.11b/g/n WLAN bands.
32 nRESET input Active-low global device reset; use an RC network (100kΩ
33 VDD_PA_IN power_in Supply for the RF power amplifier (PA).
34 SOP1 input Sense-on-power bit 1 used for factory restore; add a 100kΩ pulldown to ground; also used for 5GHz switch control.
35 SOP0 input Sense-on-power bit 0 used for factory restore; add a 100kΩ pulldown to ground; also used for 5GHz switch control.
36 LDO_IN1 power_in Input to the internal LDO, fed from the analog DC/DC output.
37 VIN_DCDC_ANA power_in Power supply input for the analog DC/DC converter; absolute maximum 3.8 V with respect to VSS.
38 DCDC_ANA_SW power_out Analog DC/DC converter switching node output.
39 VIN_DCDC_PA power_in Input supply for the PA DC/DC converter; absolute maximum 3.8 V with respect to VSS.
40 DCDC_PA_SW_P power_out PA DC/DC converter positive switching node output.
41 DCDC_PA_SW_N power_out PA DC/DC converter negative switching node output.
42 DCDC_PA_OUT power_out PA DC/DC converter output; connect the DC/DC output capacitor here.
43 DCDC_DIG_SW power_out Digital DC/DC converter switching node output.
44 VIN_DCDC_DIG power_in Power supply input for the digital DC/DC converter; absolute maximum 3.8 V with respect to VSS.
45 DIO31 bidirectional Digital input or output; Network Scripter I/O, with LPDS retention unavailable.
46 DCDC_ANA2_SW_N power_out Analog2 DC/DC converter negative switching node output.
47 VDD_ANA2 power_in Analog2 power supply input.
48 VDD_ANA1 power_in Analog1 power supply input.
49 VDD_RAM power_in Power supply for the internal RAM (internal SRAM LDO output per the signal table).
50 UART1_nRTS output UART1 host interface request-to-send, active low.
51 RTC_XTAL_P passive 32.768kHz crystal XTAL_P connection, or external CMOS-level clock input.
52 RTC_XTAL_N passive 32.768kHz crystal XTAL_N connection, or a 100kΩ pullup to the supply when an external clock is used.
53 DIO30 bidirectional Digital input or output; Network Scripter I/O.
54 VIN_IO2 power_in I/O power supply input, same as battery voltage (VBAT).
55 UART1_TX output UART host interface TX; connect to a test point on prototypes for flash programming.
56 VDD_DIG2 power_in Digital power supply, 1.2 V.
57 UART1_RX input UART host interface RX; connect to a test point on prototypes for flash programming.
58 TEST_58 output Test signal; connect to an external test point.
59 TEST_59 input Test signal; connect to an external test point.
60 TEST_60 output Test signal; connect to an external test point.
61 UART1_nCTS input UART1 clear-to-send input, active low.
62 TEST_62 output Test signal; connect to an external test point.
63 DIO8 bidirectional Digital input or output, multiplexed with antenna-select control, hostless-mode I/O and BLE/2.4GHz coexistence I/O.
64 DIO9 bidirectional Digital input or output, multiplexed with antenna-select control, hostless-mode I/O and BLE/2.4GHz coexistence I/O.
65 GND power_in Ground thermal and electrical tab; connect to ground.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64(9x9)
Category Radio Frequency Chip/Antenna
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage, VBAT and VIO pins (absolute maximum) -0.5 3.8 V Pins 37, 39, 44 16
Digital inputs (absolute maximum) -0.5 V 16
RF pins (absolute maximum) -0.5 2.1 V 16
Analog pins, crystal pins (absolute maximum) -0.5 2.1 V Pins 22, 23, 51, 52 16
Operating temperature TA -40 85 °C 16
Storage temperature Tstg -55 125 °C 16
Supply voltage VBAT, VIO (recommended) 2.1 3.3 3.6 V Direct battery connection; pins 10, 37, 39, 44, 54 16
Ambient thermal slew -20 20 °C/minute 16
Low-level input voltage (DIO pins except 52, 53) VIL -0.5 V TA = 25°C, VBAT = 2.1V to 3.3V 21
Pullup current IOH 5 10 µA TA = 25°C, VBAT = 3.0V; VOH = 2.4 (VDD = 3.0V) 23
Transmit center frequency accuracy -25 25 ppm Channel 6 (2437MHz) 24
Operating frequency range 2412 2472 MHz 24
TX current, 1 DSSS 272 mA TA = 25°C, VBAT = 3.6V; TX power level = 0 17
TX current, 1 DSSS 188 mA TA = 25°C, VBAT = 3.6V; TX power level = 4 17
TX current, 6 OFDM 248 mA TA = 25°C, VBAT = 3.6V; TX power level = 0 17
TX current, 6 OFDM 179 mA TA = 25°C, VBAT = 3.6V; TX power level = 4 17
TX current, 54 OFDM 223 mA TA = 25°C, VBAT = 3.6V; TX power level = 0 17
TX current, 54 OFDM 160 mA TA = 25°C, VBAT = 3.6V; TX power level = 4 17
RX current, 1 DSSS 53 mA TA = 25°C, VBAT = 3.6V 17
RX current, 54 OFDM 53 mA TA = 25°C, VBAT = 3.6V 17
Idle connected current 690 µA TA = 25°C, VBAT = 3.6V; DTIM = 1 17
LPDS current 115 µA TA = 25°C, VBAT = 3.6V 17
Hibernate current 4 µA TA = 25°C, VBAT = 3.6V 17
Shutdown current 1 µA TA = 25°C, VBAT = 3.6V 17
Peak calibration current 420 mA TA = 25°C, VBAT = 3.6V 17
Peak calibration current 450 mA TA = 25°C, VBAT = 3.3V 17
Peak calibration current 670 mA TA = 25°C, VBAT = 2.1V 17
Pin capacitance (DIO except 52, 53) CIN 4 pF TA = 25°C, VBAT = 2.1V to 3.3V 21
High-level input current (DIO except 52, 53) IIH 5 nA TA = 25°C, VBAT = 2.1V to 3.3V 21
Low-level input current (DIO except 52, 53) IIL 5 nA TA = 25°C, VBAT = 2.1V to 3.3V 21
Pin capacitance (DIO 52, 53) CIN 7 pF TA = 25°C, VBAT = 2.1V to 3.6V 22
High-level input current (DIO 52, 53) IIH 50 nA TA = 25°C, VBAT = 2.1V to 3.6V 22
Low-level input current (DIO 52, 53) IIL 50 nA TA = 25°C, VBAT = 2.1V to 3.6V 22
Low-level input voltage nRESET VIL 0.6 V TA = 25°C, VBAT = 2.1V to 3.6V 23
Pulldown current IOL 5 µA TA = 25°C, VBAT = 3.0V; VOL = 0.4 (VDD = 3.0V) 23
Sensitivity, 1 DSSS -96 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz); 8% PER 23
Sensitivity, 2 DSSS -94 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz); 8% PER 23
Sensitivity, 11 CCK -88 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz); 8% PER 23
Sensitivity, 6 OFDM -90.5 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz); 10% PER 23
Sensitivity, 9 OFDM -90 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz); 10% PER 23
Sensitivity, 18 OFDM -86.5 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz); 10% PER 23
Sensitivity, 36 OFDM -80.5 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz); 10% PER 23
Sensitivity, 54 OFDM -74.5 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz); 10% PER 23
Sensitivity, MCS7 (GF) -71.5 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz); 10% PER 23
Maximum input level, 802.11b -4 dBm 10% PER 23
Maximum input level, 802.11g -10 dBm 10% PER 23
Maximum RMS output power, 1 DSSS 18 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz) 24
Maximum RMS output power, 2 DSSS 18 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz) 24
Maximum RMS output power, 11 CCK 18.3 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz) 24
Maximum RMS output power, 6 OFDM 17.3 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz) 24
Maximum RMS output power, 9 OFDM 17.3 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz) 24
Maximum RMS output power, 18 OFDM 17 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz) 24
Maximum RMS output power, 36 OFDM 16 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz) 24
Maximum RMS output power, 54 OFDM 14.5 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz) 24
Maximum RMS output power, MCS7 13 dBm TA = 25°C, VBAT = 2.1V to 3.6V; channel 6 (2437MHz) 24
Junction-to-case thermal resistance RΘJC 6.3 °C/W Airflow 0.0051 m/s 25
Junction-to-board thermal resistance RΘJB 2.4 °C/W Airflow 0.0051 m/s 25
Junction-to-free air thermal resistance RΘJA 23 °C/W Airflow 0.0051 m/s 25

CAD (KiCad official)

  • Symbol: CC3130RNMRGKR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: cc3130rnmrgkr-etched.step / cc3130rnmrgkr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cc3130rnmrgkr.step / cc3130rnmrgkr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (76 pp, sha256 bb94220da2dafe4f, retrieved 2026-10-31, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF