component

CC2544RHBR

Public Made by Adom

by adom

Texas Instruments RF Transceiver ICs, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrf and wirelesscc2544rhbrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers cc2544rhbr: viewers · Ray 2d ago
cc2544rhbr-etched.glb cc2544rhbr: factory component page (tier=lcsc) · Ray 2d ago
cc2544rhbr-etched.step cc2544rhbr: factory component page (tier=lcsc) · Ray 2d ago
cc2544rhbr-hero.glb Publish 0.1.0 · Ray 2d ago
cc2544rhbr-hero.overlay.json Publish 0.1.0 · Ray 2d ago
cc2544rhbr.glb Publish 0.1.0 · Ray 2d ago
cc2544rhbr.kicad_mod Publish 0.1.0 · Ray 2d ago
cc2544rhbr.kicad_sym Publish 0.1.0 · Ray 2d ago
cc2544rhbr.lbr Publish 0.1.0 · Ray 2d ago
cc2544rhbr.step Publish 0.1.0 · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Initial commit: component/cc2544rhbr · Ray 2d ago

CC2544RHBR

Texas Instruments · RF Transceiver ICs · VQFN-32-EP(5x5)

CC2544RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 USB_P bidirectional USB D+ line of the full-speed USB 2.0 module, with internal pull-up for D+.
2 USB_N bidirectional USB D- line of the full-speed USB 2.0 module.
3 VDD power_in AVDD analog supply pin, 2 V to 3.6 V, must be at the same voltage as all other VDD pins.
4 DCPL2 passive 3.3-V regulator decoupling pin.
5 VBUS power_in 5-V power input for the optional on-chip 5 V to 3.3 V regulator, operating range 4 V to 5.45 V.
6 P1_0 bidirectional General-purpose I/O port 1 bit 0 with 20 mA drive strength.
7 P1_1 bidirectional General-purpose I/O port 1 bit 1 with 20 mA drive strength.
8 VDD power_in IOVDD digital I/O supply pin, 2 V to 3.6 V, must be at the same voltage as all other VDD pins.
9 P0_0 bidirectional General-purpose I/O port 0 bit 0.
10 P0_1 bidirectional General-purpose I/O port 0 bit 1.
11 VSS power_in Optional IOVSS ground pin.
12 VDD power_in IOVDD digital I/O supply pin, 2 V to 3.6 V, must be at the same voltage as all other VDD pins.
13 P0_2 bidirectional General-purpose I/O port 0 bit 2.
14 P0_3 bidirectional General-purpose I/O port 0 bit 3.
15 RESET_N input Active-low reset input.
16 VDD power_in AVDD analog supply pin, 2 V to 3.6 V, must be at the same voltage as all other VDD pins.
17 XOSC1 input 32-MHz crystal oscillator pin 1 or external-clock input.
18 XOSC2 passive 32-MHz crystal oscillator pin 2.
19 VDD power_in AVDD analog supply pin, 2 V to 3.6 V, must be at the same voltage as all other VDD pins.
20 RF_P bidirectional Positive RF input to the LNA during RX and positive RF output from the PA during TX.
21 RF_N bidirectional Negative RF input to the LNA during RX and negative RF output from the PA during TX.
22 VDD power_in AVDD analog supply pin, 2 V to 3.6 V, must be at the same voltage as all other VDD pins.
23 VDD power_in AVDD analog supply pin, 2 V to 3.6 V, must be at the same voltage as all other VDD pins.
24 VDD power_in AVDD analog supply pin, 2 V to 3.6 V, must be at the same voltage as all other VDD pins.
25 RBIAS passive External precision bias resistor connection for reference current.
26 VDD power_in AVDD_GUARD supply pin, 2 V to 3.6 V, must be at the same voltage as all other VDD pins.
27 VSS power_in Optional IOVSS ground pin.
28 P1_2 bidirectional General-purpose I/O port 1 bit 2, also the debug clock.
29 P1_3 bidirectional General-purpose I/O port 1 bit 3, also the debug data.
30 VDD power_in IOVDD digital I/O supply pin, 2 V to 3.6 V, must be at the same voltage as all other VDD pins.
31 DCPL1 passive 1.8-V regulator decoupling pin.
32 VSS power_in USB ground pin.
33 VSS power_in Exposed thermal pad, must be connected to a solid ground plane as the main ground connection for the chip.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category RF And Wireless
Pins 33

CAD (KiCad official)

  • Symbol: CC2544RHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: cc2544rhbr-etched.step / cc2544rhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cc2544rhbr.step / cc2544rhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 553344b3091742a9, retrieved 2026-10-03, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF