component
CC2540F256RHAR
Public Made by Adomby adom
Texas Instruments RF Transceiver ICs, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCC2540F256RHAR
Texas Instruments · RF Transceiver ICs · WQFN-40-EP(6x6)
CC2540F256RHAR from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DGND_USB | power_in | USB ground pin; connect to GND. |
| 2 | USB_P | bidirectional | USB D+ differential data line for the full-speed USB interface. |
| 3 | USB_N | bidirectional | USB D- differential data line for the full-speed USB interface. |
| 4 | DVDD_USB | power_in | 2 V to 3.6 V digital power-supply connection for the USB interface. |
| 5 | P1_5 | bidirectional | General-purpose digital I/O, Port 1.5. |
| 6 | P1_4 | bidirectional | General-purpose digital I/O, Port 1.4. |
| 7 | P1_3 | bidirectional | General-purpose digital I/O, Port 1.3. |
| 8 | P1_2 | bidirectional | General-purpose digital I/O, Port 1.2. |
| 9 | P1_1 | bidirectional | General-purpose digital I/O, Port 1.1, with 20-mA drive capability. |
| 10 | DVDD2 | power_in | 2 V to 3.6 V digital power-supply connection. |
| 11 | P1_0 | bidirectional | General-purpose digital I/O, Port 1.0, with 20-mA drive capability. |
| 12 | P0_7 | bidirectional | General-purpose digital I/O, Port 0.7. |
| 13 | P0_6 | bidirectional | General-purpose digital I/O, Port 0.6. |
| 14 | P0_5 | bidirectional | General-purpose digital I/O, Port 0.5. |
| 15 | P0_4 | bidirectional | General-purpose digital I/O, Port 0.4. |
| 16 | P0_3 | bidirectional | General-purpose digital I/O, Port 0.3. |
| 17 | P0_2 | bidirectional | General-purpose digital I/O, Port 0.2. |
| 18 | P0_1 | bidirectional | General-purpose digital I/O, Port 0.1. |
| 19 | P0_0 | bidirectional | General-purpose digital I/O, Port 0.0. |
| 20 | RESET_N | input | Active-low chip reset input; minimum low-pulse duration of 1 µs for a complete reset. |
| 21 | AVDD5 | power_in | 2 V to 3.6 V analog power-supply connection; VDD reference for the ADC input voltage on this pin. |
| 22 | XOSC_Q1 | passive | 32-MHz crystal oscillator pin 1, or external-clock input. |
| 23 | XOSC_Q2 | passive | 32-MHz crystal oscillator pin 2. |
| 24 | AVDD3 | power_in | 2 V to 3.6 V analog power-supply connection. |
| 25 | RF_P | bidirectional | Positive RF input signal to the LNA during RX, and positive RF output signal from the PA during TX. |
| 26 | RF_N | bidirectional | Negative RF input signal to the LNA during RX, and negative RF output signal from the PA during TX. |
| 27 | AVDD2 | power_in | 2 V to 3.6 V analog power-supply connection. |
| 28 | AVDD1 | power_in | 2 V to 3.6 V analog power-supply connection. |
| 29 | AVDD4 | power_in | 2 V to 3.6 V analog power-supply connection. |
| 30 | RBIAS | passive | External precision bias resistor connection used for reference current generation. |
| 31 | AVDD6 | power_in | 2 V to 3.6 V analog power-supply connection. |
| 32 | P2_4/XOSC32K_Q1 | bidirectional | General-purpose digital I/O Port 2.4, alternatively the 32.768-kHz crystal oscillator pin 1 (analog I/O). |
| 33 | P2_3/XOSC32K_Q2 | bidirectional | General-purpose digital I/O Port 2.3, alternatively the 32.768-kHz crystal oscillator pin 2 (analog I/O). |
| 34 | P2_2 | bidirectional | General-purpose digital I/O, Port 2.2; also used as debug clock line in the two-wire debug interface. |
| 35 | P2_1 | bidirectional | General-purpose digital I/O, Port 2.1; also used as debug data line in the two-wire debug interface. |
| 36 | P2_0 | bidirectional | General-purpose digital I/O, Port 2.0. |
| 37 | P1_7 | bidirectional | General-purpose digital I/O, Port 1.7. |
| 38 | P1_6 | bidirectional | General-purpose digital I/O, Port 1.6. |
| 39 | DVDD1 | power_in | 2 V to 3.6 V digital power-supply connection. |
| 40 | DCOUPL | power_out | 1.8-V digital power-supply decoupling node for the internal digital regulator; do not use to supply external circuits. |
| 41 | GND | power_in | Exposed die-attach/ground pad; must be soldered to a solid ground plane as it forms the chip's ground connection. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-40-EP(6x6) |
| Category | RF And Wireless |
| Pins | 41 |
CAD (KiCad official)
- Symbol:
CC2540F256RHAR - Footprint:
Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm - 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
cc2540f256rhar-etched.step/cc2540f256rhar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cc2540f256rhar.step/cc2540f256rhar.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (36 pp, sha256
2c8f3edd5c0452e5, retrieved 2026-09-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).