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CC2540F128RHAR

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Texas Instruments RF Transceiver ICs, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs cc2540f128rhar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cc2540f128rhar: viewers · Ray
cc2540f128rhar-etched.fit.json cc2540f128rhar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cc2540f128rhar-etched.glb cc2540f128rhar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cc2540f128rhar-etched.step cc2540f128rhar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cc2540f128rhar.glb Publish 0.1.0 · Ray
cc2540f128rhar.kicad_mod Publish 0.1.0 · Ray
cc2540f128rhar.kicad_sym Publish 0.1.0 · Ray
cc2540f128rhar.lbr Publish 0.1.0 · Ray
cc2540f128rhar.step Publish 0.1.0 · Ray
package.json cc2540f128rhar: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
page.json cc2540f128rhar: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md Initial commit: component/cc2540f128rhar · Ray

CC2540F128RHAR

Texas Instruments · RF Transceiver ICs · VQFN-40-EP(6x6)

CC2540F128RHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DGND_USB power_in USB ground pin; must be connected to GND.
2 USB_P bidirectional USB D+ full-speed differential signal pin.
3 USB_N bidirectional USB D− full-speed differential signal pin.
4 DVDD_USB power_in 2-V to 3.6-V digital power-supply connection for USB.
5 P1_5 bidirectional General-purpose digital I/O port 1, bit 5; 4-mA drive.
6 P1_4 bidirectional General-purpose digital I/O port 1, bit 4; 4-mA drive.
7 P1_3 bidirectional General-purpose digital I/O port 1, bit 3; 4-mA drive.
8 P1_2 bidirectional General-purpose digital I/O port 1, bit 2; 4-mA drive.
9 P1_1 bidirectional General-purpose digital I/O port 1, bit 1; 20-mA drive capability.
10 DVDD2 power_in 2-V to 3.6-V digital power-supply connection.
11 P1_0 bidirectional General-purpose digital I/O port 1, bit 0; 20-mA drive capability.
12 P0_7 bidirectional General-purpose digital I/O port 0, bit 7; 4-mA drive.
13 P0_6 bidirectional General-purpose digital I/O port 0, bit 6; 4-mA drive.
14 P0_5 bidirectional General-purpose digital I/O port 0, bit 5; 4-mA drive.
15 P0_4 bidirectional General-purpose digital I/O port 0, bit 4; 4-mA drive.
16 P0_3 bidirectional General-purpose digital I/O port 0, bit 3; 4-mA drive.
17 P0_2 bidirectional General-purpose digital I/O port 0, bit 2; 4-mA drive.
18 P0_1 bidirectional General-purpose digital I/O port 0, bit 1; 4-mA drive.
19 P0_0 bidirectional General-purpose digital I/O port 0, bit 0; 4-mA drive.
20 RESET_N input Active-low reset input; minimum recognisable pulse width 1 µs.
21 AVDD5 power_in 2-V to 3.6-V analog power-supply connection.
22 XOSC_Q1 passive 32-MHz crystal oscillator pin 1 or external-clock input; CL 10-16 pF, ESR max 60 Ω.
23 XOSC_Q2 passive 32-MHz crystal oscillator pin 2; CL 10-16 pF, ESR max 60 Ω.
24 AVDD3 power_in 2-V to 3.6-V analog power-supply connection.
25 RF_P bidirectional Positive RF port - LNA input during RX, PA output during TX; optimum differential load impedance 70+j30 Ω.
26 RF_N bidirectional Negative RF port - LNA input during RX, PA output during TX; optimum differential load impedance 70+j30 Ω.
27 AVDD2 power_in 2-V to 3.6-V analog power-supply connection.
28 AVDD1 power_in 2-V to 3.6-V analog power-supply connection.
29 AVDD4 power_in 2-V to 3.6-V analog power-supply connection.
30 RBIAS passive External precision bias resistor connection for internal reference current; 56 kΩ recommended.
31 AVDD6 power_in 2-V to 3.6-V analog power-supply connection.
32 P2_4/XOSC32K_Q1 bidirectional Digital I/O port 2, bit 4, or 32.768-kHz crystal oscillator pin 1; CL 12-16 pF.
33 P2_3/XOSC32K_Q2 bidirectional Digital I/O port 2, bit 3, or 32.768-kHz crystal oscillator pin 2; CL 12-16 pF.
34 P2_2 bidirectional General-purpose digital I/O port 2, bit 2; also serves as DEBUG_CLK when debug interface is active.
35 P2_1 bidirectional General-purpose digital I/O port 2, bit 1; also serves as DEBUG_DATA when debug interface is active.
36 P2_0 bidirectional General-purpose digital I/O port 2, bit 0; 4-mA drive.
37 P1_7 bidirectional General-purpose digital I/O port 1, bit 7; 4-mA drive.
38 P1_6 bidirectional General-purpose digital I/O port 1, bit 6; 4-mA drive.
39 DVDD1 power_in 2-V to 3.6-V digital power-supply connection.
40 DCOUPL power_out Output of the on-chip 1.8-V digital voltage regulator; requires 1-µF external decoupling capacitor; must not supply external circuits.
41 GND power_in Exposed thermal pad; must be soldered to a solid ground plane - this is the primary ground connection for the device.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-40-EP(6x6)
Category RF And Wireless
Pins 41

CAD (KiCad official)

  • Symbol: CC2540F128RHAR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: cc2540f128rhar-etched.step / cc2540f128rhar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cc2540f128rhar.step / cc2540f128rhar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 2c8f3edd5c0452e5, retrieved 2026-09-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF