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docs cc2538nf53rtqr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cc2538nf53rtqr: viewers · Ray
cc2538nf53rtqr-etched.fit.json cc2538nf53rtqr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cc2538nf53rtqr-etched.glb cc2538nf53rtqr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cc2538nf53rtqr-etched.step cc2538nf53rtqr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cc2538nf53rtqr.glb Publish 0.1.0 · Ray
cc2538nf53rtqr.kicad_mod Publish 0.1.0 · Ray
cc2538nf53rtqr.kicad_sym Publish 0.1.0 · Ray
cc2538nf53rtqr.lbr Publish 0.1.0 · Ray
cc2538nf53rtqr.step Publish 0.1.0 · Ray
package.json cc2538nf53rtqr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
page.json cc2538nf53rtqr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md Initial commit: component/cc2538nf53rtqr · Ray

CC2538NF53RTQR

Texas Instruments · RF Transceiver ICs · QFN-56-EP(8x8)

CC2538NF53RTQR from Texas Instruments, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DGND_USB power_in USB ground connection.
2 USB_P bidirectional USB differential data plus (D+) signal line.
3 USB_N bidirectional USB differential data minus (D-) signal line.
4 DVDD_USB power_in 3.3-V USB power-supply connection.
5 PB0 bidirectional GPIO port B pin 0.
6 PC7 bidirectional GPIO port C pin 7.
7 PC6 bidirectional GPIO port C pin 6.
8 PC5 bidirectional GPIO port C pin 5.
9 PC4 bidirectional GPIO port C pin 4.
10 DVDD power_in 2-V-3.6-V digital power-supply connection.
11 PC3 bidirectional GPIO port C pin 3, 20 mA output capability, no pull-up or pull-down.
12 PC2 bidirectional GPIO port C pin 2, 20 mA output capability, no pull-up or pull-down.
13 PC1 bidirectional GPIO port C pin 1, 20 mA output capability, no pull-up or pull-down.
14 PC0 bidirectional GPIO port C pin 0, 20 mA output capability, no pull-up or pull-down.
15 DVDD power_in 2-V-3.6-V digital power-supply connection.
16 PA0 bidirectional GPIO port A pin 0; can also serve as ROM bootloader UART RXD.
17 PA1 bidirectional GPIO port A pin 1; can also serve as ROM bootloader UART TXD.
18 PA2 bidirectional GPIO port A pin 2; can also serve as ROM bootloader SSI CLK.
19 PA3 bidirectional GPIO port A pin 3; can also serve as ROM bootloader SSI SEL.
20 PA4 bidirectional GPIO port A pin 4; can also serve as ROM bootloader SSI RXD.
21 PA5 bidirectional GPIO port A pin 5; can also serve as ROM bootloader SSI TXD.
22 PA6 bidirectional GPIO port A pin 6.
23 PA7 bidirectional GPIO port A pin 7.
24 DVDD power_in 2-V-3.6-V digital power-supply connection.
25 PD0 bidirectional GPIO port D pin 0.
26 PD1 bidirectional GPIO port D pin 1.
27 PD2 bidirectional GPIO port D pin 2.
28 RESET_N input Active-low reset input; minimum pulse width 1 µs.
29 PD3 bidirectional GPIO port D pin 3.
30 PD4 bidirectional GPIO port D pin 4.
31 PD5 bidirectional GPIO port D pin 5.
32 DCOUPL2 power_in 1.8-V regulated digital-supply decoupling capacitor connection; short to pin 56.
33 AVDD power_in 2-V-3.6-V analog power-supply connection.
34 XOSC32M_Q1 bidirectional 32-MHz crystal oscillator pin 1 or external-clock input.
35 XOSC32M_Q2 bidirectional 32-MHz crystal oscillator pin 2.
36 AVDD power_in 2-V-3.6-V analog power-supply connection.
37 RF_P bidirectional Positive RF input to LNA during RX; positive RF output from PA during TX.
38 RF_N bidirectional Negative RF input to LNA during RX; negative RF output from PA during TX.
39 AVDD power_in 2-V-3.6-V analog power-supply connection.
40 AVDD power_in 2-V-3.6-V analog power-supply connection.
41 AVDD power_in 2-V-3.6-V analog power-supply connection.
42 R_BIAS bidirectional External precision bias resistor for reference current.
43 AVDD_GUARD power_in 2-V-3.6-V analog power-supply connection for guard.
44 PD6/XOSC32K_Q1 bidirectional GPIO port D pin 6 or 32-kHz crystal oscillator pin 1.
45 PD7/XOSC32K_Q2 bidirectional GPIO port D pin 7 or 32-kHz crystal oscillator pin 2.
46 JTAG_TMS input JTAG test mode select input.
47 JTAG_TCK input JTAG test clock input.
48 PB7 bidirectional GPIO port B pin 7; can also serve as JTAG TDO.
49 PB6 bidirectional GPIO port B pin 6; can also serve as JTAG TDI.
50 PB5 bidirectional GPIO port B pin 5.
51 PB4 bidirectional GPIO port B pin 4.
52 PB3 bidirectional GPIO port B pin 3.
53 PB2 bidirectional GPIO port B pin 2.
54 PB1 bidirectional GPIO port B pin 1.
55 DVDD power_in 2-V-3.6-V digital power-supply connection.
56 DCOUPL1 power_in 1.8-V regulated digital-supply decoupling capacitor connection.
57 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-56-EP(8x8)
Category RF And Wireless
Pins 57

CAD (KiCad official)

  • Symbol: CC2538NF53RTQR
  • Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • 3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: cc2538nf53rtqr-etched.step / cc2538nf53rtqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cc2538nf53rtqr.step / cc2538nf53rtqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 5e1df6df95278fed, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF