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Ray Initial commit: component/cc1350f128rsmr f2ec2e8

CC1350F128RSMR

Texas Instruments · RF Transceiver ICs · VQFN-32-EP(4x4)

CC1350F128RSMR from Texas Instruments, in a VQFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RF_P bidirectional Positive RF I/O: positive RF input signal to the LNA during RX and positive RF output signal from the PA during TX.
2 RF_N bidirectional Negative RF I/O: negative RF input signal to the LNA during RX and negative RF output signal from the PA during TX.
3 VSS power_in Ground pin.
4 RX_TX bidirectional Optional bias pin for the RF LNA (RF I/O).
5 X32K_Q1 passive 32-kHz crystal oscillator pin 1, analog I/O for the optional low-frequency crystal.
6 X32K_Q2 passive 32-kHz crystal oscillator pin 2, analog I/O for the optional low-frequency crystal.
7 VSS power_in Ground pin.
8 DIO_0 bidirectional General-purpose digital I/O with Sensor Controller connectivity and high-drive capability.
9 DIO_1 bidirectional General-purpose digital I/O with Sensor Controller connectivity and high-drive capability.
10 DIO_2 bidirectional General-purpose digital I/O with Sensor Controller connectivity and high-drive capability.
11 VDDS2 power_in 1.8-V to 3.8-V GPIO supply for the associated DIO pins.
12 DCOUPL power_out 1.27-V regulated digital-supply decoupling capacitor pin; do not supply external circuitry from this pin.
13 JTAG_TMSC bidirectional JTAG TMSC debug signal, digital I/O.
14 JTAG_TCKC bidirectional JTAG TCKC debug signal, digital I/O; noise-immunity design considerations apply per the JTAG Interface chapter of the TRM.
15 DIO_3 bidirectional General-purpose digital I/O with high-drive capability, alternately usable as JTAG_TDO.
16 DIO_4 bidirectional General-purpose digital I/O with high-drive capability, alternately usable as JTAG_TDI.
17 VSS power_in Ground pin.
18 DCDC_SW power_out Switching output pin from the internal DC/DC converter.
19 VDDS_DCDC power_in 1.8-V to 3.8-V DC/DC supply input pin.
20 VSS power_in Ground pin.
21 RESET_N input Active-low reset input; no internal pullup is present.
22 DIO_5 bidirectional General-purpose digital or analog I/O with Sensor Controller connectivity and analog capability.
23 DIO_6 bidirectional General-purpose digital or analog I/O with Sensor Controller connectivity and analog capability.
24 DIO_7 bidirectional General-purpose digital or analog I/O with Sensor Controller connectivity and analog capability.
25 DIO_8 bidirectional General-purpose digital or analog I/O with Sensor Controller connectivity and analog capability.
26 DIO_9 bidirectional General-purpose digital or analog I/O with Sensor Controller connectivity and analog capability.
27 VDDS power_in 1.8-V to 3.8-V main chip supply.
28 VDDR power_in 1.7-V to 1.95-V supply; connect to output of internal DC/DC, or to the main LDO if the DC/DC is not used.
29 VSS power_in Ground pin.
30 X24M_N passive 24-MHz crystal oscillator pin 1, analog I/O.
31 X24M_P passive 24-MHz crystal oscillator pin 2, analog I/O.
32 VDDR_RF power_in 1.7-V to 1.95-V supply; must connect to VDDR for supply from the main LDO if the internal DC/DC is not used.
33 EGP power_in Exposed ground pad on the package underside; must be soldered to the PCB ground plane for proper thermal and mechanical performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(4x4)
Category RF And Wireless
Pins 33

CAD (KiCad official)

  • Symbol: CC1350F128RSMR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: VQFN-32-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: cc1350f128rsmr-etched.step / cc1350f128rsmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cc1350f128rsmr.step / cc1350f128rsmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (76 pp, sha256 9d1e8bc21bd619c6, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF