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CC1310F128RHBR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs cc1310f128rhbr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cc1310f128rhbr: viewers · Ray
cc1310f128rhbr-etched.fit.json cc1310f128rhbr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cc1310f128rhbr-etched.glb cc1310f128rhbr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cc1310f128rhbr-etched.step cc1310f128rhbr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cc1310f128rhbr.glb Publish 0.1.0 · Ray
cc1310f128rhbr.kicad_mod Publish 0.1.0 · Ray
cc1310f128rhbr.kicad_sym Publish 0.1.0 · Ray
cc1310f128rhbr.lbr Publish 0.1.0 · Ray
cc1310f128rhbr.step Publish 0.1.0 · Ray
package.json cc1310f128rhbr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
page.json cc1310f128rhbr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md Initial commit: component/cc1310f128rhbr · Ray

CC1310F128RHBR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-32-EP(5x5)

CC1310F128RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RF_P passive Positive differential RF port; positive RF input signal to LNA during RX and positive RF output signal from PA during TX; maximum input RF level 10 dBm.
2 RF_N passive Negative differential RF port; negative RF input signal to LNA during RX and negative RF output signal from PA during TX; maximum input RF level 10 dBm.
3 RX_TX passive Optional external bias pin for the RF LNA.
4 X32K_Q1 passive 32-kHz crystal oscillator pin 1; supports 32.768-kHz watch crystal with CL = 6-12 pF and ESR ≤ 100 kΩ.
5 X32K_Q2 passive 32-kHz crystal oscillator pin 2; supports 32.768-kHz watch crystal with CL = 6-12 pF and ESR ≤ 100 kΩ.
6 DIO_0 bidirectional General-purpose digital I/O, Sensor Controller capable; VIH = 0.8×VDDS2, VIL = 0.2×VDDS2.
7 DIO_1 bidirectional General-purpose digital I/O, Sensor Controller capable; VIH = 0.8×VDDS2, VIL = 0.2×VDDS2.
8 DIO_2 bidirectional General-purpose digital I/O with high-drive capability, Sensor Controller capable; VOH = 2.68 V and VOL = 0.33 V at 8-mA load (VDDS2 = 3.0 V).
9 DIO_3 bidirectional General-purpose digital I/O with high-drive capability, Sensor Controller capable; VOH = 2.68 V and VOL = 0.33 V at 8-mA load (VDDS2 = 3.0 V).
10 DIO_4 bidirectional General-purpose digital I/O with high-drive capability, Sensor Controller capable; VOH = 2.68 V and VOL = 0.33 V at 8-mA load (VDDS2 = 3.0 V).
11 VDDS2 power_in 1.8-V to 3.8-V GPIO supply for DIO_0-DIO_6 and JTAG pins; must be ≥ 1.9 V when VDDS ≥ 2.7 V.
12 DCOUPL power_out 1.27-V regulated digital-supply decoupling node; connect external bypass capacitor only; do not supply external circuitry from this pin.
13 JTAG_TMSC bidirectional JTAG/cJTAG TMSC bidirectional serial data pin with high-drive capability; used for IEEE 1149.7 cJTAG or IEEE 1149.1 JTAG debug interface.
14 JTAG_TCKC input JTAG/cJTAG TCKC clock input; noise-immunity precautions required per JTAG Interface chapter of the CC13x0 Technical Reference Manual.
15 DIO_5 bidirectional General-purpose digital I/O with high-drive capability; alternate function JTAG_TDO; VOH = 2.68 V and VOL = 0.33 V at 8-mA load (VDDS = 3.0 V).
16 DIO_6 bidirectional General-purpose digital I/O with high-drive capability; alternate function JTAG_TDI; VOH = 2.68 V and VOL = 0.33 V at 8-mA load (VDDS = 3.0 V).
17 DCDC_SW power_out Switching output node of the internal DC/DC converter; do not supply external circuitry from this pin.
18 VDDS_DCDC power_in 1.8-V to 3.8-V supply input to the internal DC/DC converter; must be connected to the same voltage as VDDS.
19 RESET_N input Active-low reset input; no internal pullup; minimum low pulse duration 1 µs.
20 DIO_7 bidirectional General-purpose digital I/O with analog capability, Sensor Controller capable; one of up to eight ADC-capable GPIO pins.
21 DIO_8 bidirectional General-purpose digital I/O with analog capability, Sensor Controller capable; one of up to eight ADC-capable GPIO pins.
22 DIO_9 bidirectional General-purpose digital I/O with analog capability, Sensor Controller capable; one of up to eight ADC-capable GPIO pins.
23 DIO_10 bidirectional General-purpose digital I/O with analog capability, Sensor Controller capable; one of up to eight ADC-capable GPIO pins.
24 DIO_11 bidirectional General-purpose digital I/O with analog capability, Sensor Controller capable; one of up to eight ADC-capable GPIO pins.
25 DIO_12 bidirectional General-purpose digital I/O with analog capability, Sensor Controller capable; one of up to eight ADC-capable GPIO pins.
26 DIO_13 bidirectional General-purpose digital I/O with analog capability, Sensor Controller capable; one of up to eight ADC-capable GPIO pins.
27 DIO_14 bidirectional General-purpose digital I/O with analog capability, Sensor Controller capable; one of up to eight ADC-capable GPIO pins.
28 VDDS power_in 1.8-V to 3.8-V main chip supply; powers DIO_7-DIO_14 and RESET_N domain; rising slew rate ≤ 100 mV/µs, falling ≤ 20 mV/µs.
29 VDDR power_in 1.7-V to 1.95-V regulated digital core supply; connect to output of internal DC/DC converter; if DC/DC not used, supplied internally from main LDO; do not supply external circuitry.
30 X24M_N passive 24-MHz crystal oscillator pin 1; required frequency reference for the radio; supports CL = 5-9 pF and ESR ≤ 60 Ω (CL 6-9 pF).
31 X24M_P passive 24-MHz crystal oscillator pin 2; required frequency reference for the radio; supports CL = 5-9 pF and ESR ≤ 60 Ω (CL 6-9 pF).
32 VDDR_RF power_in 1.7-V to 1.95-V RF core supply; connect to output of internal DC/DC; if DC/DC not used, must be connected to VDDR; do not supply external circuitry.
33 EGP power_in Exposed ground pad; must be soldered to PCB ground plane for optimal thermal and mechanical performance; RθJC(bottom) = 1.9 °C/W.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Embedded Processors & Controllers
Pins 33

CAD (KiCad official)

  • Symbol: CC1310F128RHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: cc1310f128rhbr-etched.step / cc1310f128rhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cc1310f128rhbr.step / cc1310f128rhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (72 pp, sha256 2303c92927169c1e, retrieved 2026-09-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF