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CC1125RHBT

Texas Instruments · RF Transceiver ICs · VQFN-32-EP(5x5)

CC1125RHBT from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD_GUARD	power_in	Guard supply pin, powered from 2.0-3.6 V VDD.
2	RESET_N	input	Asynchronous, active-low digital reset input.
3	GPIO3	bidirectional	General-purpose digital I/O.
4	GPIO2	bidirectional	General-purpose digital I/O.
5	DVDD	power_in	2.0-3.6 V VDD supply to the internal digital regulator.
6	DCPL	passive	Digital regulator output to external decoupling capacitor.
7	SI	input	Serial data in (SPI).
8	SCLK	input	Serial data clock (SPI).
9	SO(GPIO1)	bidirectional	Serial data out (SPI), also usable as general-purpose I/O.
10	GPIO0	bidirectional	General-purpose digital I/O.
11	CSn	input	Active-low chip select for the SPI interface.
12	DVDD	power_in	2.0-3.6 V VDD supply.
13	AVDD_IF	power_in	2.0-3.6 V VDD supply for the IF section.
14	RBIAS	passive	Connection for an external high-precision resistor.
15	AVDD_RF	power_in	2.0-3.6 V VDD supply for the RF section.
16	N.C.	unconnected	Not connected.
17	PA	output	Single-ended TX output; requires a DC path to VDD.
18	TRX_SW	passive	TX and RX switch; connected internally to GND in TX and floating (high-impedance) in RX.
19	LNA_P	input	Differential RX input; requires a DC path to GND.
20	LNA_N	input	Differential RX input; requires a DC path to GND.
21	DCPL_VCO	passive	Pin for external decoupling of the VCO supply regulator.
22	AVDD_SYNTH1	power_in	2.0-3.6 V VDD supply for the synthesizer.
23	LPF0	passive	Connection for external loop filter components.
24	LPF1	passive	Connection for external loop filter components.
25	AVDD_PFD_CHP	power_in	2.0-3.6 V VDD supply for the PFD and charge pump.
26	DCPL_PFD_CHP	passive	Pin for external decoupling of the PFD and CHP regulator.
27	AVDD_SYNTH2	power_in	2.0-3.6 V VDD supply for the synthesizer.
28	AVDD_XOSC	power_in	2.0-3.6 V VDD supply for the crystal oscillator.
29	DCPL_XOSC	passive	Pin for external decoupling of the XOSC supply regulator.
30	XOSC_Q1	passive	Crystal oscillator pin 1; must be grounded if a TCXO or other external clock on EXT_XOSC is used.
31	XOSC_Q2	passive	Crystal oscillator pin 2; must be left floating if a TCXO or other external clock on EXT_XOSC is used.
32	EXT_XOSC	input	External clock input; must be grounded if a regular crystal is connected to XOSC_Q1 and XOSC_Q2.
33	GND	power_in	Ground pad; must be connected to a solid ground plane.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-32-EP(5x5)
Category	Radio Frequency Chip/Antenna
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage (VDD, AVDD_x)		-0.3		3.9	V	All supply pins must have the same voltage	7
Input RF level				10	dBm		7
Voltage on any digital pin		-0.3		3.9	V	VDD+0.3, max 3.9	7
Voltage on analog pins (including DCPL pins)		-0.3		2	V		7
Solder reflow temperature				260	°C	According to IPC/JEDEC J-STD-020	7
Storage temperature range	Tstg	-40		125	°C		7
ESD HBM	VESD	-2		2	kV	HBM per ANSI/ESDA/JEDEC JS001, all pins	7
ESD CDM	VESD	-500		500	V	CDM per JESD22-C101, all pins	7
Voltage supply range		2		3.6	V	All supply pins must have the same voltage	7
Voltage on digital inputs		0			V	max VDD	7
Temperature range		-40		85	°C	Ambient	7
Junction-to-free air thermal resistance	RθJA		31.3		°C/W	Air flow 0.00 m/s	7
Junction-to-case (top)	RθJC		21.1		°C/W	Air flow 0.00 m/s	7
Junction-to-board	RθJB		5.3		°C/W	Air flow 0.00 m/s	7
Junction-to-case (bottom)	RθJC		0.8		°C/W	Air flow 0.00 m/s	7
Junction-to-package top	PsiJT		0.2		°C/W	Air flow 0.00 m/s	7
Frequency band		820		960	MHz		8
Frequency band		410		480	MHz		8
Frequency band		164		192	MHz		8
Data rate		0		200	kbps	Packet mode	8
Data rate		0		100	kbps	Transparent mode	8
Power down with retention current			0.12	1	µA	TA = 25°C, VDD = 3.0 V, fxosc = 32 MHz	9
Digital channel filter programmable bandwidth		2.8		200	kHz	fxosc = 32 MHz	11
Digital channel filter programmable bandwidth		3.5		250	kHz	fxosc = 40 MHz	11
Datarate offset tolerance		-12		12	%	With carrier sense detection enabled and assuming 4-byte preamble	11
Datarate offset tolerance		-0.2		0.2	%	With carrier sense detection disabled	11
Crystal frequency		32		44	MHz		19
ESR				50	Ω	<50	19
TCXO clock frequency		32		44	MHz		19
TCXO CMOS high input voltage		1.4			V	CMOS output directly coupled to EXT_OSC; max VDD	19
TCXO CMOS low input voltage				0.6	V	CMOS output directly coupled to EXT_OSC	19
Clipped sine clock input amplitude (peak-to-peak)		0.8		1.5	V	Clipped sine TCXO via series capacitor	19
32-kHz clock input high voltage		0.8			V	0.8×VDD	19
32-kHz clock input low voltage				0.2	V	0.2×VDD	19
Frequency accuracy after calibration		-0.1		0.1	%	Relative to frequency reference	20
Logic input high voltage		0.8			V	0.8×VDD	20
Logic input low voltage				0.2	V	0.2×VDD	20
Logic output high voltage		0.8			V	0.8×VDD, at 4-mA output load or less	20
Logic output low voltage				0.2	V	0.2×VDD, at 4-mA output load or less	20
Temperature sensor range		-40		85	°C		20
Power down current, RC oscillator running			0.5		µA	Low-power RC oscillator running	9
XOFF mode current			170		µA	Crystal oscillator / TCXO disabled	9
IDLE mode current			1.3		mA	Clock running, system waiting with no radio activity	9
TX current consumption +14 dBm, 868/915/920 MHz			47		mA	TA = 25°C, VDD = 3.0 V, fxosc = 40 MHz	9
TX current consumption +10 dBm, 868/915/920 MHz			38		mA	TA = 25°C, VDD = 3.0 V, fxosc = 40 MHz	9
RX peak current, 433/868/915/920 MHz			26		mA	fxosc = 40 MHz, peak current during packet reception at sensitivity threshold	10
RX peak current low-power mode			17		mA	1.2 kbps reception at the sensitivity level	10
RX wait for sync current, RX sniff mode			2		mA	1.2 kbps, 4-byte preamble	10
Saturation			10		dBm		11
IIP3, normal mode			-14		dBm	At maximum gain	11
Power-on reset threshold			1.3		V	Voltage on DVDD pin	20

CAD (KiCad official)

Symbol: CC1125RHBT
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: cc1125rhbt-etched.step / cc1125rhbt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cc1125rhbt.step / cc1125rhbt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (38 pp, sha256 abea680a01c90aee, retrieved 2026-10-23, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF