Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

CBMuD1200HAS8

Corebai Microelectronics · Digital Isolators · SOIC-8

CBMuD1200HAS8 from Corebai Microelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Side 1 supply, 2.5V to 5.5V operating range, with a 0.01uF-0.1uF bypass capacitor to GND1.
2 VIA input Logic input of channel A on side 1, with VIH min 0.7xVDD and VIL max 0.3xVDD.
3 VIB input Logic input of channel B on side 1, with VIH min 0.7xVDD and VIL max 0.3xVDD.
4 GND1 power_in Ground reference for side 1.
5 GND2 power_in Ground reference for side 2.
6 VOB output Logic output of channel B on side 2, driven from the VIB input (CBMuD1200 is unidirectional).
7 VOA output Logic output of channel A on side 2, driven from the VIA input (CBMuD1200 is unidirectional).
8 VDD2 power_in Side 2 supply, 2.5V to 5.5V operating range, with a 0.01uF-0.1uF bypass capacitor to GND2.

Key specifications

Parameter Value
Manufacturer Corebai Microelectronics
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (operating) VDD 2.5 5.5 V Operating 2
Rated dielectric isolation voltage 3000 V RMS 持续 1 分钟 2
Minimum external creepage 3.9 mm 测量输入端至输出端,沿壳体最短距离 2
Minimum PCB layer clearance 3.9 mm PCB 各层电源域最短距离 2
Supply voltage VCC -0.3 6 V 2
I/O supply voltage VIO -0.3 6 V GND-0.3 to VCC+0.5 2
I/O port max output current IO -50 50 mA 2
Junction temperature TJ 150 ℃ 2
Storage temperature TS -50 150 ℃ 2
ESD HBM VESD-HBM -3000 3000 V Human Body Model, per ANSI/ESDA/JEDEC JS-001 2
ESD CDM VESD-CDM -500 500 V Charged Device Model, per JEDEC specification JESD22-C101 2
Data rate DR 50 MHz VDD1=VDD2 = 5V 4
Minimum pulse width PW 10 ns VDD1=VDD2 = 5V 4
Propagation delay high to low tPHL 5 8 ns 50%输入至 50%输出, VDD1=VDD2 = 5V 4
Propagation delay low to high tPLH 5 8 ns 50%输入至 50%输出, VDD1=VDD2 = 5V 4
Propagation delay high to low tPHL 7 12 ns 50%输入至 50%输出, VDD1=VDD2 = 3.3V 3
Propagation delay high to low tPHL 10 13 ns 50%输入至 50%输出, VDD1=VDD2 = 2.5V 3
Operating temperature -40 125 ℃ Ordering table, CBMuD1200HAS8 6

CAD (KiCad official)

  • Symbol: CBMuD1200HAS8
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: cbmud1200has8-etched.step / cbmud1200has8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cbmud1200has8.step / cbmud1200has8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Corebai Microelectronics datasheet (6 pp, sha256 43769f995e61c202, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF