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CBM8656AS8

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Corebai Microelectronics Precision Op Amps, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CBM8656AS8

Corebai Microelectronics · Precision Op Amps · SOIC-8

CBM8656AS8 from Corebai Microelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT A output Amplifier A output; rail-to-rail swing, output current ±220 mA at VS=5V, short-circuit to GND indefinite.
2 -IN A input Amplifier A inverting input; rail-to-rail, keep within VSS−0.3V to VDD+0.3V and limit input current to under 5 mA.
3 +IN A input Amplifier A non-inverting input; rail-to-rail, keep within VSS−0.3V to VDD+0.3V and limit input current to under 5 mA.
4 V- power_in Negative supply (ground in single-supply use); bypass with 0.1 µF close to the package.
5 +IN B input Amplifier B non-inverting input; rail-to-rail, keep within VSS−0.3V to VDD+0.3V and limit input current to under 5 mA.
6 -IN B input Amplifier B inverting input; rail-to-rail, keep within VSS−0.3V to VDD+0.3V and limit input current to under 5 mA.
7 OUT B output Amplifier B output; rail-to-rail swing, output current ±220 mA at VS=5V, short-circuit to GND indefinite.
8 V+ power_in Positive supply, 2.7 V to 5.5 V operation (absolute maximum 6 V); bypass with 0.1 µF close to the package.

Key specifications

Parameter Value
Manufacturer Corebai Microelectronics
Package SOIC-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Offset Voltage VOS 50 250 µV VS=5.0V; VCM=0V to 5V 3
Offset Voltage (over temperature) 550 µV VS=5.0V; −40°C≤TA≤+125℃ 3
Offset Voltage Drift ΔVOS/ΔT 0.4 2.3 µV/℃ VS=5.0V; −40°C≤TA≤+125℃ 3
Input Bias Current IB 1 10 pA VS=5.0V 3
Input Bias Current (over temperature) 500 pA VS=5.0V; −40°C≤TA≤+125℃ 3
Input Voltage Range 0 5 V VS=5.0V 3
Common-Mode Rejection Ratio CMRR 85 100 dB VS=5.0V; VCM=0V to 5V 3
Large Signal Voltage Gain AVO 100 110 dB VS=5.0V; VO=0.2V to 4.8V, RL=10kΩ, VCM=0V 3
Large Signal Voltage Gain (over temperature) AVO 95 dB VS=5.0V; −40°C≤TA≤+125°C 3
Output Voltage High VOH 4.97 4.991 V VS=5.0V; IL=1mA;−40℃≤TA≤+125℃ 3
Output Voltage Low VOL 8 30 mV VS=5.0V; IL=1mA;−40℃≤TA≤+125℃ 3
Output Current VOUT -220 220 mA VS=5.0V; VOUT=±0.5V 3
Power Supply Rejection Ratio PSRR 88 105 dB VS=2.7V to 5.0V 3
Supply Current/Amplifier ISY 3.7 4.5 mA VS=5.0V; VO=0V 3
Supply Current/Amplifier (over temperature) 5.3 mA VS=5.0V; −40℃≤TA≤+125℃ 3
Offset Voltage VOS 44 250 µV VS=2.7V; VCM=0V to 2.7V 5
Offset Voltage (over temperature) 550 µV VS=2.7V; −40℃≤TA≤+125℃ 5
Offset Voltage Drift ΔVOS/ΔT 0.4 2 µV/℃ VS=2.7V; −40℃≤TA≤+125℃ 5
Input Bias Current IB 1 10 pA VS=2.7V 5
Input Bias Current (over temperature) 500 pA VS=2.7V; −40℃≤TA≤+125℃ 5
Input Voltage Range 0 2.7 V VS=2.7V 5
Common-Mode Rejection Ratio CMRR 80 98 dB VS=2.7V; VCM=0V to 2.7V 5
Large Signal Voltage Gain AVO 98 dB VS=2.7V; VO=0.2V to 2.5V, RL=10kΩ, VCM=0V 5
Large Signal Voltage Gain (over temperature) AVO 90 dB VS=2.7V; −40℃≤TA≤+125℃ 5
Output Voltage High VOH 2.67 2.688 V VS=2.7V; IL=1mA;−40℃≤TA≤+125℃ 5
Output Voltage Low VOL 10 30 mV VS=2.7V; IL=1mA;−40℃≤TA≤+125℃ 5
Output Current VOUT -75 75 mV VS=2.7V; VOUT=±0.5V 5
Supply Current/Amplifier ISY 3.7 4.5 mA VS=2.7V; VO=0V 5
Supply Current/Amplifier (over temperature) 5.3 mA VS=2.7V; −40℃≤TA≤+125℃ 5
Supply Voltage 6 V 6
Differential Input Voltage -6 6 V 6
Electrostatic Discharge (HBM) 3 kV 6
Storage Temperature Range -65 150 ℃ R, RM Packages 6
Junction Temperature Range -65 150 ℃ R, RM Packages 6
Lead Temperature (Soldering) 260 ℃ Soldering, 10 sec 6
Thermal Resistance Junction-to-Ambient (8-Lead SOIC, R) θJA 158 ℃/W 6
Thermal Resistance Junction-to-Case (8-Lead SOIC, R) θJC 43 ℃/W 6
Supply Voltage (operating) 2.7 5.5 V 2.7 V to 5.5 V operation 1
Operating Temperature Range -40 125 ℃ −40°C to +125°C operation 1

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC Poor PC board layout, contaminants, and the board insulator material can create leakage 22

CAD (KiCad official)

  • Symbol: CBM8656AS8
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: cbm8656as8-etched.step / cbm8656as8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cbm8656as8.step / cbm8656as8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Corebai Microelectronics datasheet (25 pp, sha256 29c3f6721613b5a4, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF