component
CBM8552AS8
Public Made by Adomby adom
Corebai Microelectronics Precision Op Amps, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
CBM8552AS8
Corebai Microelectronics · Precision Op Amps · SOIC-8
CBM8552AS8 from Corebai Microelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTA | output | Amplifier A output, rail-to-rail swing. |
| 2 | INA- | input | Amplifier A inverting input, rail-to-rail with common-mode range from VSS-0.1V to VDD+0.1V. |
| 3 | INA+ | input | Amplifier A non-inverting input, rail-to-rail with common-mode range from VSS-0.1V to VDD+0.1V. |
| 4 | VSS | power_in | Negative supply or ground; for dual-supply operation, bypass with a 0.1µF ceramic capacitor. |
| 5 | INB+ | input | Amplifier B non-inverting input, rail-to-rail with common-mode range from VSS-0.1V to VDD+0.1V. |
| 6 | INB- | input | Amplifier B inverting input, rail-to-rail with common-mode range from VSS-0.1V to VDD+0.1V. |
| 7 | OUTB | output | Amplifier B output, rail-to-rail swing. |
| 8 | VDD | power_in | Positive supply, 1.8V to 5.5V single supply (absolute max 7.5V VDD to VSS); place a 0.1µF ceramic capacitor close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Corebai Microelectronics |
| Package | SOIC-8 |
| Category | Amplifiers/Comparators |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Supply Voltage (VDD to VSS) | -0.5 | 7.5 | V | 3 | |||
| Analog Input Voltage (IN+ or IN-) | -0.5 | 0.5 | V | Printed as VSS-0.5V (min) and VDD+0.5V (max); values are offsets from the supply rails, not absolute volts | 3 | ||
| PDB Input Voltage | -0.5 | 7 | V | Printed as VSS-0.5V (min) and +7V (max); min is rail-referenced | 3 | ||
| Operating Temperature Range | -45 | 125 | ℃ | 3 | |||
| Junction Temperature | 160 | ℃ | 3 | ||||
| Storage Temperature Range | -55 | 150 | ℃ | 3 | |||
| Lead Temperature (soldering) | 260 | ℃ | soldering, 10 sec | 3 | |||
| Package Thermal Resistance SOP-8 | θJA | 125 | ℃/W | TA=+25℃ | 3 | ||
| Supply Voltage (single supply) | 1.8 | 5.5 | V | Single supply; dual supply ±0.9V to ±2.75V per application notes | 7 | ||
| Operating Temperature Range | -45 | 125 | ℃ | Ordering table lists -40℃~125℃ for this part | 1 | ||
| Input Offset Voltage | VOS | 1 | 30 | μV | 4 | ||
| Output Voltage Low, RL to +VS | VOL | 2 | mV | RL = 100kΩ to +VS | 4 | ||
| Output Voltage Low, RL to +VS | VOL | 5 | mV | RL = 10kΩ to +VS | 4 | ||
| Input Bias Current | IB | 20 | pA | 4 | |||
| Input Offset Current | IOS | 10 | pA | 4 | |||
| Common-Mode Rejection Ratio | CMRR | 110 | dB | VCM = 0V to 5V | 4 | ||
| Large Signal Voltage Gain | AVO | 145 | dB | RL = 10kΩ, VO = 0.3V to 4.7V | 4 | ||
| Input Offset Voltage Drift | ∆VOS/∆T | 30 | nV/℃ | 4 | |||
| Output Voltage High, RL to -VS | VOH | 4.998 | V | RL = 100kΩ to -VS | 4 | ||
| Output Voltage High, RL to -VS | VOH | 4.994 | V | RL = 10kΩ to -VS | 4 | ||
| Short Circuit Limit | ISC | 60 | mA | RL = 10Ω to -VS | 4 | ||
| Output Current | IO | 65 | mA | 4 | |||
| Power Supply Rejection Ratio | PSRR | 115 | dB | VS = 2.5V to 5.5V | 4 | ||
| Quiescent Current | IQ | 180 | μA | VO = 0V, RL = 0Ω | 4 | ||
| Gain-Bandwidth Product | GBP | 1.8 | MHz | G = +100 | 4 | ||
| Slew Rate | SR | 0.95 | V/μs | RL = 10kΩ | 4 | ||
| Overload Recovery Time | 0.1 | ms | 4 | ||||
| Voltage Noise (en p-p) | en p-p | 0.3 | μVp-p | 0Hz to 10Hz | 4 | ||
| Voltage Noise Density | en | 38 | nV/√Hz | f = 1kHz | 4 |
CAD (KiCad official)
- Symbol:
CBM8552AS8 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
cbm8552as8-etched.step/cbm8552as8-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cbm8552as8.step/cbm8552as8.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Corebai Microelectronics datasheet (16 pp, sha256
f2188dc09cf52931, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CBM8552AS8
**Corebai Microelectronics** · Precision Op Amps · SOIC-8
CBM8552AS8 from Corebai Microelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTA | output | Amplifier A output, rail-to-rail swing. |
| 2 | INA- | input | Amplifier A inverting input, rail-to-rail with common-mode range from VSS-0.1V to VDD+0.1V. |
| 3 | INA+ | input | Amplifier A non-inverting input, rail-to-rail with common-mode range from VSS-0.1V to VDD+0.1V. |
| 4 | VSS | power_in | Negative supply or ground; for dual-supply operation, bypass with a 0.1µF ceramic capacitor. |
| 5 | INB+ | input | Amplifier B non-inverting input, rail-to-rail with common-mode range from VSS-0.1V to VDD+0.1V. |
| 6 | INB- | input | Amplifier B inverting input, rail-to-rail with common-mode range from VSS-0.1V to VDD+0.1V. |
| 7 | OUTB | output | Amplifier B output, rail-to-rail swing. |
| 8 | VDD | power_in | Positive supply, 1.8V to 5.5V single supply (absolute max 7.5V VDD to VSS); place a 0.1µF ceramic capacitor close to the pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Corebai Microelectronics |
| Package | SOIC-8 |
| Category | Amplifiers/Comparators |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Supply Voltage (VDD to VSS) | | -0.5 | | 7.5 | V | | 3 |
| Analog Input Voltage (IN+ or IN-) | | -0.5 | | 0.5 | V | Printed as VSS-0.5V (min) and VDD+0.5V (max); values are offsets from the supply rails, not absolute volts | 3 |
| PDB Input Voltage | | -0.5 | | 7 | V | Printed as VSS-0.5V (min) and +7V (max); min is rail-referenced | 3 |
| Operating Temperature Range | | -45 | | 125 | ℃ | | 3 |
| Junction Temperature | | | | 160 | ℃ | | 3 |
| Storage Temperature Range | | -55 | | 150 | ℃ | | 3 |
| Lead Temperature (soldering) | | | | 260 | ℃ | soldering, 10 sec | 3 |
| Package Thermal Resistance SOP-8 | θJA | | 125 | | ℃/W | TA=+25℃ | 3 |
| Supply Voltage (single supply) | | 1.8 | | 5.5 | V | Single supply; dual supply ±0.9V to ±2.75V per application notes | 7 |
| Operating Temperature Range | | -45 | | 125 | ℃ | Ordering table lists -40℃~125℃ for this part | 1 |
| Input Offset Voltage | VOS | | 1 | 30 | μV | | 4 |
| Output Voltage Low, RL to +VS | VOL | | | 2 | mV | RL = 100kΩ to +VS | 4 |
| Output Voltage Low, RL to +VS | VOL | | | 5 | mV | RL = 10kΩ to +VS | 4 |
| Input Bias Current | IB | | 20 | | pA | | 4 |
| Input Offset Current | IOS | | 10 | | pA | | 4 |
| Common-Mode Rejection Ratio | CMRR | | 110 | | dB | VCM = 0V to 5V | 4 |
| Large Signal Voltage Gain | AVO | | 145 | | dB | RL = 10kΩ, VO = 0.3V to 4.7V | 4 |
| Input Offset Voltage Drift | ∆VOS/∆T | | 30 | | nV/℃ | | 4 |
| Output Voltage High, RL to -VS | VOH | | 4.998 | | V | RL = 100kΩ to -VS | 4 |
| Output Voltage High, RL to -VS | VOH | | 4.994 | | V | RL = 10kΩ to -VS | 4 |
| Short Circuit Limit | ISC | | 60 | | mA | RL = 10Ω to -VS | 4 |
| Output Current | IO | | 65 | | mA | | 4 |
| Power Supply Rejection Ratio | PSRR | | 115 | | dB | VS = 2.5V to 5.5V | 4 |
| Quiescent Current | IQ | | 180 | | μA | VO = 0V, RL = 0Ω | 4 |
| Gain-Bandwidth Product | GBP | | 1.8 | | MHz | G = +100 | 4 |
| Slew Rate | SR | | 0.95 | | V/μs | RL = 10kΩ | 4 |
| Overload Recovery Time | | | 0.1 | | ms | | 4 |
| Voltage Noise (en p-p) | en p-p | | 0.3 | | μVp-p | 0Hz to 10Hz | 4 |
| Voltage Noise Density | en | | 38 | | nV/√Hz | f = 1kHz | 4 |
## CAD (KiCad official)
- Symbol: `CBM8552AS8`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `cbm8552as8-etched.step` / `cbm8552as8-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cbm8552as8.step` / `cbm8552as8.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Corebai Microelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884873846640640) (16 pp, sha256 `f2188dc09cf52931`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cbm8552as8-datasheet.pdf)