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CBM812SST4

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Corebai Microelectronics Supervisor And Reset ICs, SOT-143-4. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CBM812SST4

Corebai Microelectronics · Supervisor And Reset ICs · SOT-143-4

CBM812SST4 from Corebai Microelectronics, in a SOT-143-4. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Power supply ground, 0 V reference for the device.
2 RESET output For the CBM812 variant this is the active-high reset output: it is driven high while reset is asserted, and remains active for 240 ms (typical) after VCC rises above the reset threshold (2.93 V typical for the CBM812S).
3 MR input Manual reset input with built-in debounce: input transitions shorter than 100 ns are ignored and inputs held longer than 10 µs reliably trigger a reset.
4 VCC power_in Monitored supply voltage input (2.5 V, 3 V, 3.3 V or 5 V nominal, per the suffix); the device operates from 1.0 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Corebai Microelectronics
Package SOT-143-4
Category Power Management (PMIC)
Pins 4

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range 1 5.5 V 5
Typical VCC for S variant VCC 3.3 V CBM811S/CBM812S nominal VCC 5
Supply current 8 15 μA 5
Reset threshold (CBM812S) 2.88 2.93 2.98 V TA = −40°C to +85°C 5
Reset threshold (CBM812S), second limit row 2.85 3 V TA = −40°C to +85°C 5
Manual reset minimum pulse width 10 μs MR input pulse to trigger reset 5
Manual reset glitch immunity 100 ns MR pulses shorter than this are ignored 5
Manual reset propagation delay 0.5 μs 5
Manual reset pull-up resistor 10 20 30 kΩ 5
MR input high threshold 2.3 V MR input greater than 5
MR input low threshold 0.8 V MR input less than 5
Power-up reset timeout 140 ms 1
Reset output active time after VCC rises above threshold 240 ms after VCC above reset threshold 8
VCC terminal voltage VCC -0.3 6 V relative to GND 4
Input voltage range -0.3 V upper limit VCC + 0.3 V 4
VCC input current 20 mA 4
MR input current 20 mA 4
RESET output current 20 mA 4
Power dissipation 200 mW TA = 70 °C, SOT-143 4
Power derating 4 mW/°C above TA = 70 °C 4
Thermal resistance, junction-to-ambient θJA 330 °C/W 4
Operating temperature range -40 85 °C 4
Storage temperature range -65 160 °C 4
Lead temperature (soldering) 300 °C 10 s 4
Lead temperature (vapor phase) 215 °C 60 s 4
Lead temperature (infrared) 220 °C 15 s 4
ESD rating 3 kV model not specified 4

CAD (KiCad official)

  • Symbol: CBM812SST4
  • Footprint: Package_TO_SOT_SMD:SOT-143
  • 3D model: SOT-143-4 (KiCad packages3D, STEP)
  • 3D model files: cbm812sst4-etched.step / cbm812sst4-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cbm812sst4.step / cbm812sst4.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Corebai Microelectronics datasheet (10 pp, sha256 47b7db87adfeaa64, retrieved 2026-10-21, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF