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CBM708TAS8

Public Made by Adom

by adom

Corebai Microelectronics Supervisor And Reset ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CBM708TAS8

Corebai Microelectronics · Supervisor And Reset ICs · SOIC-8

CBM708TAS8 from Corebai Microelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Manual reset input: when taken below 0.6 V a RESET/RESET pulse is generated, and the input is internally debounced with an internal 70 µA pull-up that holds it high when floating.
2 VCC power_in Power supply input; place a 0.1 µF decoupling capacitor between the VCC and GND pins.
3 GND power_in Ground reference for all signals (0 V).
4 PFI input Power fail input, the noninverting input to the power fail comparator; when PFI is below 1.25 V, PFO goes low, and if unused PFI must connect to GND.
5 PFO output Power fail output from the power fail comparator, which goes low when PFI is less than 1.25 V.
6 NC unconnected No connect.
7 RESET output Active-low logic output that goes low for 200 ms when triggered by VCC below the reset threshold or a low on MR, stays low while VCC is below threshold, and remains low 200 ms after VCC rises above threshold or MR goes high; a watchdog timeout does not trigger it unless WDO is connected to MR.
8 RESET output Active-high logic output for systems using active-high reset logic; it is the inverse of RESET.

Key specifications

Parameter Value
Manufacturer Corebai Microelectronics
Package SOIC-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC Operating Voltage Range VCC 1 5.5 V 3
Supply Current IQ 100 200 μA VCC < 3.6 V 3
Supply Current IQ 150 μA VCC < 5.5 V 3
Reset Threshold (CBM708T) VRST 3 3.08 3.15 V CBM706T/CBM708T 3
RESET Pulse Width 160 200 280 ms 3
RESET Output VOH (RESET, CBM708T) VOH 0.8 ×VCC VRST(max)<VCC<3.6V, ISOURCE=500μA 3
RESET Output VOL (RESET, CBM708T) VOL 0.3 V VRST(max)<VCC<3.6V, ISINK=1.2mA 3
RESET Output VOH (RESET, CBM708T) VOH -1.5 V offset from VCC 4.5V<VCC<5.5V, ISOURCE=800μA 3
RESET Output VOL (RESET, CBM708T) VOL 0.4 V 4.5V<VCC<5.5V, ISINK=3.2mA 3
RESET Output VOH (RESET active high, CBM708T) VOH 0.8 ×VCC VRST(max)<VCC<3.6V, ISOURCE=500μA 3
RESET Output VOL (RESET active high, CBM708T) VOL 0.3 V VRST(max)<VCC<3.6V, ISINK=500μA 3
RESET Output VOH (RESET active high, CBM708T) VOH -1.5 V offset from VCC 4.5V<VCC<5.5V, ISOURCE=800μA 3
RESET Output VOL (RESET active high, CBM708T) VOL 0.4 V 4.5V<VCC<5.5V, ISINK=1.2mA 3
Manual Reset (MR) Pull-Up Current 25 70 250 μA MR=0V, VRST(max)<VCC<3.6V 4
Manual Reset (MR) Pull-Up Current 100 250 600 μA MR=0V, 4.5V<VCC<5.5V 4
MR Pulse Width 500 ns VRST(max)<VCC<3.6V 4
MR Pulse Width 150 ns 4.5V<VCC<5.5V 4
MR Input Threshold VIL VIL 0.6 V VRST(max)<VCC<3.6V 4
MR Input Threshold VIH VIH 0.7 ×VCC VRST(max)<VCC<3.6V 4
MR Input Threshold VIL VIL 0.8 V 4.5V<VCC<5.5V 4
MR Input Threshold VIH VIH 2 V 4.5V<VCC<5.5V 4
MR to RESET Output Delay 750 ns VRST(max)<VCC<3.6V 4
MR to RESET Output Delay 250 ns 4.5V<VCC<5.5V 4
PFI Input Threshold 1.2 1.25 1.3 V CBM706S/CBM708S/CBM706T/CBM708T, VCC=3.3V, PFI falling 4
PFI Input Current -25 0.01 25 nA 4
PFO Output VOH VOH 0.8 ×VCC VRST(max)<VCC<3.6V, ISOURCE=500μA 4
PFO Output VOL VOL 0.3 V VRST(max)<VCC<3.6V, ISINK=1.2mA 4
PFO Output VOH VOH -1.5 V offset from VCC 4.5V<VCC<5.5V, ISOURCE=800μA 4
PFO Output VOL VOL 0.4 V 4.5V<VCC<5.5V, ISINK=3.2mA 4
VCC Supply Voltage (absolute maximum) VCC -0.3 6 V 5
All Other Inputs Voltage (absolute maximum) -0.3 0.3 V above VCC Relative to VCC (printed VCC+0.3V) 5
Input Current (VCC pin) 20 mA VCC pin 5
Input Current (GND pin) 20 mA GND pin 5
Digital Output Current 20 mA 5
Power Dissipation (R-8 SOIC) PD 470 mW R-8 SOIC 5
Operating Temperature Range (Industrial, Version A) TA -40 85 ℃ Industrial (Version A) 5
Storage Temperature Range TSTG -65 150 ℃ 5
Lead Temperature (Soldering) 300 ℃ Soldering, 10 sec 5
Lead Temperature (Vapor Phase) 215 ℃ Vapor phase, 60 sec 5
Lead Temperature (Infrared) 220 ℃ Infrared, 15 sec 5
ESD Rating 4.5 kV 5
Thermal Impedance θJA (R-8 SOIC) θJA 110 ℃/W R-8 SOIC 5
Supply Voltage for CBM708T (VCC = 3.15 V to 5.5 V) VCC 3.15 5.5 V CBM70XT variant, TA = TMIN to TMAX 3
Power Fail Input / Reset Hysteresis 20 mV 3

CAD (KiCad official)

  • Symbol: CBM708TAS8
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: cbm708tas8-etched.step / cbm708tas8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cbm708tas8.step / cbm708tas8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Corebai Microelectronics datasheet (19 pp, sha256 9a448ecfa70d44be, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF