CBM706RAS8

{
  "schema_version": 1,
  "type": "component",
  "slug": "cbm706ras8",
  "title": "CBM706RAS8",
  "brief": "Corebai Microelectronics Supervisor and Reset ICs, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "pmic",
    "cbm706ras8"
  ],
  "component": {
    "mpn": "CBM706RAS8",
    "manufacturer": "Corebai Microelectronics",
    "package": "SOP-8",
    "pin_count": 8,
    "category": "PMIC",
    "subcategory": "Supervisor and Reset ICs",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/1cf66579178283be99b685786634135c.pdf",
    "parts": {
      "symbol": "cbm706ras8.kicad_sym",
      "footprint": "cbm706ras8.kicad_mod",
      "model_3d": "cbm706ras8-etched.glb",
      "model_3d_plain": "cbm706ras8.glb",
      "model_3d_step": "cbm706ras8-etched.step",
      "model_3d_step_plain": "cbm706ras8.step",
      "lbr": "cbm706ras8.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "MR",
        "type": "input",
        "description": "Manual Reset Input (active low). When taken below 0.6 V, an active-low RESET is generated. Internally debounced; an internal 70 uA (typ.) pull-up current holds the input high when floating. Can be driven from TTL/CMOS logic or a bare switch to GND."
      },
      {
        "number": "2",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply input, 2.70 V to 5.5 V operating range (functional down to 1 V for guaranteed RESET). Place a 0.1 uF decoupling capacitor between VCC and GND. Supply current 100 uA typ. at VCC < 3.6 V."
      },
      {
        "number": "3",
        "name": "GND",
        "type": "power_in",
        "description": "Ground. 0 V reference for all signals. Absolute max sink current 20 mA."
      },
      {
        "number": "4",
        "name": "PFI",
        "type": "input",
        "description": "Power-Fail Input. Non-inverting input of the internal 1.25 V power-fail comparator. When PFI falls below 1.25 V (typ.), the PFO output is driven low. Tie to GND if unused. Input current +/-25 nA max."
      },
      {
        "number": "5",
        "name": "PFO",
        "type": "output",
        "description": "Power-Fail Output (active low). Open at PFI >= 1.25 V, driven low when PFI is below the 1.25 V threshold. VOL <= 0.3 V at ISINK = 1.2 mA; VOH >= 0.8 x VCC at ISOURCE = 500 uA (VCC < 3.6 V)."
      },
      {
        "number": "6",
        "name": "WDI",
        "type": "input",
        "description": "Watchdog Input. Each rising or falling edge on WDI clears the internal watchdog timer. If WDI stays static high or low longer than the 1.6 s (typ.) timeout, WDO goes low. Minimum WDI pulse width 100 ns (VCC < 3.6 V) / 50 ns (VCC > 4.5 V). The timer is also cleared whenever reset is asserted."
      },
      {
        "number": "7",
        "name": "RESET",
        "type": "output",
        "description": "Active-low reset output. Goes low for 200 ms (typ.) when triggered by VCC dropping below the 2.63 V reset threshold or by a low on MR. Stays low while VCC is below threshold and remains valid down to VCC = 1 V (VOL <= 0.3 V at ISINK = 100 uA). A watchdog timeout does not assert RESET unless WDO is externally tied to MR."
      },
      {
        "number": "8",
        "name": "WDO",
        "type": "output",
        "description": "Watchdog Output (active low). Goes low if the watchdog timer times out due to WDI inactivity, and also whenever VCC is below the reset threshold. Returns high as soon as VCC rises above the reset threshold and the timer is cleared. VOH >= 0.8 x VCC at ISOURCE = 500 uA; VOL <= 0.3 V at ISINK = 500 uA (VCC < 3.6 V)."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/1cf66579178283be99b685786634135c.pdf",
        "pages": 19,
        "sha256": "66ae48cae3a68e5f",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
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        "file": "cbm706ras8.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
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        "extents_mm": [
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
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        "sha256": "0e43dd5be1c265c28ad2fc9ac59f2f6e19f74d8c81ad388e79003157e60ba068",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Corebai Microelectronics",
      "Package": "SOP-8",
      "Category": "PMIC",
      "Pins": "8"
    }
  },
  "sections": [
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    "viewers",
    "readme",
    "breadcrumbs",
    "info"
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  "discovery_triggers": [
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  "discovery_pitch": "CBM706RAS8 (Corebai Microelectronics) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
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  "files": [
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    "cbm706ras8.step",
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  "visibility": {
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  "variants": [
    {
      "mpn": "CBM706RAS8",
      "kind": "packaging"
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    {
      "mpn": "CBM706RAS8N8",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-24T18:29:25.403Z"
}