component
CBM706PAS8
Public Made by Adomby adom
Corebai Microelectronics Supervisor And Reset ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CBM706PAS8
Corebai Microelectronics · Supervisor And Reset ICs · SOIC-8
CBM706PAS8 from Corebai Microelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Manual Reset input: when taken below 0.6 V a reset is generated, it is internally debounced, and an internal 70 µA pull-up holds it high when floating. |
| 2 | VCC | power_in | Power supply input; place a 0.1 µF decoupling capacitor between VCC and GND, with the device operating from 1.0 V to 5.5 V. |
| 3 | GND | power_in | Ground reference for all signals (0 V). |
| 4 | PFI | input | Power Fail Input, the noninverting input to the power fail comparator; PFO goes low when PFI is below 1.25 V, and PFI should connect to GND if unused. |
| 5 | PFO | output | Power Fail Output from the power fail comparator, which goes low when PFI is less than 1.25 V. |
| 6 | WDI | input | Watchdog Input; if WDI stays either high or low for longer than the 1.6 s watchdog timeout period, WDO goes low, and each transition on WDI resets the timer. |
| 7 | RESET | output | Active-high reset logic output (CBM706P only), the inverse of RESET, held for 200 ms after VCC rises above the reset threshold or MR goes high. |
| 8 | WDO | output | Watchdog Output that goes low when the watchdog timer times out from WDI inactivity or during low line conditions, and remains low while VCC is below the reset threshold. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Corebai Microelectronics |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC Operating Voltage Range | VCC | 1 | 5.5 | V | 3 | ||
| Supply Current | 100 | 200 | μA | VCC < 3.6 V | 3 | ||
| Supply Current | 150 | μA | VCC < 5.5 V | 3 | |||
| Reset Threshold | VRST | 2.55 | 2.63 | 2.7 | V | CBM706P/CBM706R/CBM708R | 3 |
| Reset Threshold Hysteresis | 20 | mV | 3 | ||||
| RESET Pulse Width | 160 | 200 | 280 | ms | CBM706P/CBM706R/CBM708R, VCC=3V | 3 | |
| RESET Output Voltage Low (CBM706P) | VOL | 0.3 | V | VRST(max)<VCC<3.6V, ISINK=1.2mA | 3 | ||
| RESET Output Voltage Low (CBM706P) | VOL | 0.4 | V | 4.5V<VCC<5.5V, ISINK=3.2mA | 3 | ||
| Watchdog Timeout Period | 1 | 1.6 | 2.25 | sec | CBM706P/CBM706R: VCC=3V | 3 | |
| WDI Pulse Width | 100 | ns | VRST(max)<VCC<3.6 V | 4 | |||
| WDI Pulse Width | 50 | ns | 4.5V<VCC<5.5 V | 4 | |||
| WDI Input Threshold Low | VIL | 0.6 | V | VRST(max)<VCC<3.6V | 4 | ||
| WDI Input Threshold Low | VIL | 0.8 | V | VCC=5.0V | 4 | ||
| WDI Input Threshold High | VIH | 3.5 | V | VCC=5.0V | 4 | ||
| WDI Input Current | -1 | 0.02 | 1 | μA | WDI=0V or VCC | 4 | |
| WDO Output Voltage Low | VOL | 0.3 | V | VRST(max)<VCC<3.6V, ISINK=500μA | 4 | ||
| WDO Output Voltage Low | VOL | 0.6 | V | 4.5V<VCC<5.5V, ISINK=1.2mA | 4 | ||
| MR Pull-Up Current (MR=0V) | 25 | 70 | 250 | μA | VRST(max)<VCC<3.6V | 4 | |
| MR Pull-Up Current (MR=0V) | 100 | 250 | 600 | μA | 4.5V<VCC<5.5V | 4 | |
| MR Pulse Width | 500 | ns | VRST(max)<VCC<3.6V | 4 | |||
| MR Pulse Width | 150 | ns | 4.5V<VCC<5.5V | 4 | |||
| MR Input Threshold Low | VIL | 0.6 | V | VRST(max)<VCC<3.6V | 4 | ||
| MR Input Threshold Low | VIL | 0.8 | V | 4.5V<VCC<5.5V | 4 | ||
| MR Input Threshold High | VIH | 2 | V | 4.5V<VCC<5.5V | 4 | ||
| MR to RESET Output Delay | 750 | ns | VRST(max)<VCC<3.6V | 4 | |||
| MR to RESET Output Delay | 250 | ns | 4.5V<VCC<5.5V | 4 | |||
| PFI Input Threshold | 1.2 | 1.25 | 1.3 | V | CBM706P/CBM706R/CBM708R, VCC=3V | 4 | |
| PFI Input Current | -25 | 0.01 | 25 | nA | 4 | ||
| PFO Output Voltage Low | VOL | 0.3 | V | VRST(max)<VCC<3.6V, ISINK=1.2mA | 4 | ||
| PFO Output Voltage Low | VOL | 0.4 | V | 4.5V<VCC<5.5V, ISINK=3.2mA | 4 | ||
| Supply Voltage Range (recommended) | VCC | 2.7 | 5.5 | V | CBM706P/CBM706R/CBM708R | 3 | |
| VCC Supply Voltage (absolute maximum) | VCC | -0.3 | 6 | V | TA = 25°C | 5 | |
| All Other Inputs Voltage (absolute maximum) | -0.3 | V | TA = 25°C | 5 | |||
| Input Current VCC | 20 | mA | TA = 25°C | 5 | |||
| Input Current GND | 20 | mA | TA = 25°C | 5 | |||
| Digital Output Current | 20 | mA | TA = 25°C | 5 | |||
| Power Dissipation, R-8 SOIC | 470 | mW | TA = 25°C | 5 | |||
| θJA Thermal Impedance, R-8 SOIC | θJA | 110 | ℃/W | 5 | |||
| Operating Temperature Range (Industrial, Version A) | -40 | 85 | ℃ | 5 | |||
| Lead Temperature (Soldering, 10 sec) | 300 | ℃ | 10 sec | 5 | |||
| Lead Temperature (Vapor Phase, 60 sec) | 215 | ℃ | Vapor phase, 60 sec | 5 | |||
| Lead Temperature (Infrared, 15 sec) | 220 | ℃ | Infrared, 15 sec | 5 | |||
| Storage Temperature Range | -65 | 150 | ℃ | 5 | |||
| ESD Rating | 4.5 | kV | printed as >4.5kV | 5 |
CAD (KiCad official)
- Symbol:
CBM706PAS8 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
cbm706pas8-etched.step/cbm706pas8-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cbm706pas8.step/cbm706pas8.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Corebai Microelectronics datasheet (19 pp, sha256
c45131be953a4993, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CBM706PAS8
**Corebai Microelectronics** · Supervisor And Reset ICs · SOIC-8
CBM706PAS8 from Corebai Microelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Manual Reset input: when taken below 0.6 V a reset is generated, it is internally debounced, and an internal 70 µA pull-up holds it high when floating. |
| 2 | VCC | power_in | Power supply input; place a 0.1 µF decoupling capacitor between VCC and GND, with the device operating from 1.0 V to 5.5 V. |
| 3 | GND | power_in | Ground reference for all signals (0 V). |
| 4 | PFI | input | Power Fail Input, the noninverting input to the power fail comparator; PFO goes low when PFI is below 1.25 V, and PFI should connect to GND if unused. |
| 5 | PFO | output | Power Fail Output from the power fail comparator, which goes low when PFI is less than 1.25 V. |
| 6 | WDI | input | Watchdog Input; if WDI stays either high or low for longer than the 1.6 s watchdog timeout period, WDO goes low, and each transition on WDI resets the timer. |
| 7 | RESET | output | Active-high reset logic output (CBM706P only), the inverse of RESET, held for 200 ms after VCC rises above the reset threshold or MR goes high. |
| 8 | WDO | output | Watchdog Output that goes low when the watchdog timer times out from WDI inactivity or during low line conditions, and remains low while VCC is below the reset threshold. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Corebai Microelectronics |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC Operating Voltage Range | VCC | 1 | | 5.5 | V | | 3 |
| Supply Current | | | 100 | 200 | μA | VCC < 3.6 V | 3 |
| Supply Current | | | | 150 | μA | VCC < 5.5 V | 3 |
| Reset Threshold | VRST | 2.55 | 2.63 | 2.7 | V | CBM706P/CBM706R/CBM708R | 3 |
| Reset Threshold Hysteresis | | | 20 | | mV | | 3 |
| RESET Pulse Width | | 160 | 200 | 280 | ms | CBM706P/CBM706R/CBM708R, VCC=3V | 3 |
| RESET Output Voltage Low (CBM706P) | VOL | | | 0.3 | V | VRST(max)<VCC<3.6V, ISINK=1.2mA | 3 |
| RESET Output Voltage Low (CBM706P) | VOL | | | 0.4 | V | 4.5V<VCC<5.5V, ISINK=3.2mA | 3 |
| Watchdog Timeout Period | | 1 | 1.6 | 2.25 | sec | CBM706P/CBM706R: VCC=3V | 3 |
| WDI Pulse Width | | 100 | | | ns | VRST(max)<VCC<3.6 V | 4 |
| WDI Pulse Width | | 50 | | | ns | 4.5V<VCC<5.5 V | 4 |
| WDI Input Threshold Low | VIL | | | 0.6 | V | VRST(max)<VCC<3.6V | 4 |
| WDI Input Threshold Low | VIL | | | 0.8 | V | VCC=5.0V | 4 |
| WDI Input Threshold High | VIH | 3.5 | | | V | VCC=5.0V | 4 |
| WDI Input Current | | -1 | 0.02 | 1 | μA | WDI=0V or VCC | 4 |
| WDO Output Voltage Low | VOL | | | 0.3 | V | VRST(max)<VCC<3.6V, ISINK=500μA | 4 |
| WDO Output Voltage Low | VOL | | | 0.6 | V | 4.5V<VCC<5.5V, ISINK=1.2mA | 4 |
| MR Pull-Up Current (MR=0V) | | 25 | 70 | 250 | μA | VRST(max)<VCC<3.6V | 4 |
| MR Pull-Up Current (MR=0V) | | 100 | 250 | 600 | μA | 4.5V<VCC<5.5V | 4 |
| MR Pulse Width | | 500 | | | ns | VRST(max)<VCC<3.6V | 4 |
| MR Pulse Width | | 150 | | | ns | 4.5V<VCC<5.5V | 4 |
| MR Input Threshold Low | VIL | | | 0.6 | V | VRST(max)<VCC<3.6V | 4 |
| MR Input Threshold Low | VIL | | | 0.8 | V | 4.5V<VCC<5.5V | 4 |
| MR Input Threshold High | VIH | 2 | | | V | 4.5V<VCC<5.5V | 4 |
| MR to RESET Output Delay | | | | 750 | ns | VRST(max)<VCC<3.6V | 4 |
| MR to RESET Output Delay | | | | 250 | ns | 4.5V<VCC<5.5V | 4 |
| PFI Input Threshold | | 1.2 | 1.25 | 1.3 | V | CBM706P/CBM706R/CBM708R, VCC=3V | 4 |
| PFI Input Current | | -25 | 0.01 | 25 | nA | | 4 |
| PFO Output Voltage Low | VOL | | | 0.3 | V | VRST(max)<VCC<3.6V, ISINK=1.2mA | 4 |
| PFO Output Voltage Low | VOL | | | 0.4 | V | 4.5V<VCC<5.5V, ISINK=3.2mA | 4 |
| Supply Voltage Range (recommended) | VCC | 2.7 | | 5.5 | V | CBM706P/CBM706R/CBM708R | 3 |
| VCC Supply Voltage (absolute maximum) | VCC | -0.3 | | 6 | V | TA = 25°C | 5 |
| All Other Inputs Voltage (absolute maximum) | | -0.3 | | | V | TA = 25°C | 5 |
| Input Current VCC | | | | 20 | mA | TA = 25°C | 5 |
| Input Current GND | | | | 20 | mA | TA = 25°C | 5 |
| Digital Output Current | | | | 20 | mA | TA = 25°C | 5 |
| Power Dissipation, R-8 SOIC | | | | 470 | mW | TA = 25°C | 5 |
| θJA Thermal Impedance, R-8 SOIC | θJA | | 110 | | ℃/W | | 5 |
| Operating Temperature Range (Industrial, Version A) | | -40 | | 85 | ℃ | | 5 |
| Lead Temperature (Soldering, 10 sec) | | | | 300 | ℃ | 10 sec | 5 |
| Lead Temperature (Vapor Phase, 60 sec) | | | | 215 | ℃ | Vapor phase, 60 sec | 5 |
| Lead Temperature (Infrared, 15 sec) | | | | 220 | ℃ | Infrared, 15 sec | 5 |
| Storage Temperature Range | | -65 | | 150 | ℃ | | 5 |
| ESD Rating | | 4.5 | | | kV | printed as >4.5kV | 5 |
## CAD (KiCad official)
- Symbol: `CBM706PAS8`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `cbm706pas8-etched.step` / `cbm706pas8-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cbm706pas8.step` / `cbm706pas8.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Corebai Microelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884914435866624) (19 pp, sha256 `c45131be953a4993`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cbm706pas8-datasheet.pdf)