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CBM706AS8

Corebai Microelectronics · Monitors & Reset Circuits · SOIC-8

CBM706AS8 from Corebai Microelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Active-low debounced manual reset input that generates a reset when taken below 0.8V, drivable from TTL, CMOS logic or a switch, with an internal 250μA pull-up current holding it high when floating.
2 VCC power_in 5V power supply input, with a 0.1μF decoupling capacitor placed between VCC and GND.
3 GND power_in 0V ground reference for all signals.
4 PFI input Noninverting input to the power fail comparator, which drives PFO low when PFI is below 1.25V; must be connected to GND if unused.
5 PFO output Power fail comparator output that goes low when PFI is less than 1.25V.
6 WDI input Three-level watchdog input that drives WDO low if it stays high or low longer than the watchdog timeout period (1.60 s typ), with the timer cleared by any transition and disabled when WDI is floating or connected to a three-state buffer.
7 RESET output Active-low logic output that goes low for 200ms when triggered by VCC below the 4.40V reset threshold (CBM706) or by a low on MR, and stays low while VCC is below the threshold.
8 WDO output Watchdog output that remains low until the watchdog timer is cleared, also goes low when VCC is below the reset threshold, and goes high once VCC rises above it.

Key specifications

Parameter Value
Manufacturer Corebai Microelectronics
Package SOIC-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC Operating Voltage Range VCC 1 5.5 V VCC = 4.75 V to 5.5 V, TA = TMIN to TMAX 3
Supply Current 190 250 μA 3
Reset Threshold 4.25 4.4 4.5 V CBM706/CBM708 3
Reset Threshold Hysteresis 40 mV 3
Reset Pulse Width 160 200 280 ms 3
RESET Output Voltage Low 0.4 V ISINK = 3.2 mA 3
RESET Output Voltage Low at VCC = 1 V 0.3 V VCC = 1 V, ISINK = 50 µA 3
RESET Output Voltage Low at VCC = 1.2 V 0.3 V VCC = 1.2 V, ISINK = 100 µA 3
Watchdog Timeout Period tWD 1 1.6 2.25 sec VIL = 0.4 V, VIH = VCC×0.8, WDI = VCC 3
WDI Pulse Width tWP 50 ns 3
WDI Input Threshold Logic Low 0.8 V 3
WDI Input Threshold Logic High 3.5 V 3
WDI Input Current (positive row) 50 150 µA WDI=0V 3
WDI Input Current (negative row) -150 -50 µA WDI=0V 3
WDO Output Voltage Low 0.4 V ISINK = 1.2mA 3
MR Pull-Up Current 100 250 600 µA MR = 0V 3
MR Pulse Width 150 ns 3
MR Input Threshold Logic Low 0.8 V 3
MR Input Threshold Logic High 2 V 3
MR to RESET Output Delay 250 ns 3
PFI Input Threshold 1.2 1.25 1.3 V 3
PFI Input Current -25 0.01 25 nA 3
PFO Output Voltage Low 0.4 V ISINK = 3.2 mA 3
VCC Supply Voltage VCC -0.3 6 V TA = 25°C 4
Input Current VCC 20 mA TA = 25°C 4
Input Current GND 20 mA TA = 25°C 4
Digital Output Current 20 mA TA = 25°C 4
Power Dissipation, R-8 SOIC 470 mW TA = 25°C 4
θJA Thermal Impedance, R-8 SOIC θJA 110 ℃/W 4
Operating Temperature Range (Industrial Version A) -40 85 ℃ Absolute maximum table 4
Operating Temperature Range (ordering) -40 125 ℃ CBM706AS8, SOIC-8 18
Lead Temperature (Soldering, 10 sec) 300 ℃ 4
Vapor Phase Temperature (60 sec) 215 ℃ 4
Infrared Temperature (15 sec) 220 ℃ 4
Storage Temperature Range -65 150 ℃ 4
ESD Rating 4.5 kV >4.5kV 4

CAD (KiCad official)

  • Symbol: CBM706AS8
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: cbm706as8-etched.step / cbm706as8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cbm706as8.step / cbm706as8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Corebai Microelectronics datasheet (18 pp, sha256 3801fabe2d46d615, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF