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CBM6042AS8
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Corebai Microelectronics Operational Amplifier, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CBM6042AS8
Corebai Microelectronics · Operational Amplifier · SOP-8
CBM6042AS8 from Corebai Microelectronics, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTA | output | Amplifier A output, rail-to-rail swing. |
| 2 | INA- | input | Amplifier A inverting input; common-mode range VSS-0.1V to VDD+0.1V. |
| 3 | INA+ | input | Amplifier A non-inverting input; common-mode range VSS-0.1V to VDD+0.1V. |
| 4 | VSS | power_in | Negative supply or ground; for dual supply, bypass with a 0.1uF ceramic capacitor. |
| 5 | INB+ | input | Amplifier B non-inverting input; common-mode range VSS-0.1V to VDD+0.1V. |
| 6 | INB- | input | Amplifier B inverting input; common-mode range VSS-0.1V to VDD+0.1V. |
| 7 | OUTB | output | Amplifier B output, rail-to-rail swing. |
| 8 | VDD | power_in | Positive supply, 1.4V to 5.5V; place a 0.1uF ceramic capacitor close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Corebai Microelectronics |
| Package | SOP-8 |
| Category | Amplifiers/Comparators |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Bias Current | IB | 1 | pA | 3 | |||
| Input Offset Current | IOS | 1 | pA | 3 | |||
| Common-Mode Voltage Range | VCM | -0.1 | 5.6 | V | VS = 5.5V | 3 | |
| Common-Mode Rejection Ratio | CMRR | 70 | 84 | dB | VS = 5V, VCM = -0.1V to 2.5V | 3 | |
| Common-Mode Rejection Ratio | CMRR | 67 | 83 | dB | VS = 5V, VCM = -0.1V to 5.1V | 3 | |
| Open-Loop Voltage Gain | AOL | 75 | 80 | dB | VS=1.4V, RL = 50kΩ, VO = Vs-0.1V | 3 | |
| Open-Loop Voltage Gain | AOL | 84 | 93 | dB | VS=5V, RL = 50kΩ, VO = Vs-0.1V | 3 | |
| Input Offset Voltage Drift | ΔVOS/ΔT | 25 | μV/℃ | 3 | |||
| Output Voltage Swing from Rail (high) | VOH | 1.39 | 1.395 | V | Vs=1.4V, RL = 50kΩ | 3 | |
| Output Voltage Swing from Rail (low) | VOL | 4.5 | 10 | mV | Vs=1.4V, RL = 50kΩ | 3 | |
| Output Voltage Swing from Rail (high) | VOH | 4.99 | 4.997 | V | Vs=5V, RL = 50kΩ | 3 | |
| Output Voltage Swing from Rail (low) | VOL | 3.5 | 10 | mV | Vs=5V, RL = 50kΩ | 3 | |
| Output Current (source) | ISOURCE | 45 | 60 | 84 | mA | RL = 10Ω to VS/2 | 3 |
| Output Current (sink) | ISINK | 45 | 60 | 75 | mA | RL = 10Ω to VS/2 | 3 |
| Operating Voltage Range | VS | 1.4 | 5.5 | V | 3 | ||
| Power Supply Rejection Ratio | PSRR | 77 | 80 | dB | VS=+1.4V to +5.5V, VCM=+0.5V | 3 | |
| Quiescent Current / Amplifier | IQ | 600 | nA | 3 | |||
| Gain-Bandwidth Product | GBP | 15 | KHz | CL = 100pF | 3 | ||
| Slew Rate | SR | 4.5 | V/ms | G = +1, 2V Output Step, CL = 100pF | 3 | ||
| Power Supply Voltage (VDD to VSS) | -0.5 | 7.5 | V | 2 | |||
| Operating Temperature Range | -40 | 125 | ℃ | 2 | |||
| Junction Temperature | 160 | ℃ | 2 | ||||
| Storage Temperature Range | -55 | 150 | ℃ | 2 | |||
| Lead Temperature | 260 | ℃ | soldering, 10sec | 2 | |||
| Package Thermal Resistance SOP-8 | θJA | 125 | ℃/W | TA=+25℃ | 2 | ||
| ESD Susceptibility HBM | 6 | KV | HBM | 2 | |||
| ESD Susceptibility MM | 300 | V | MM | 2 |
CAD (KiCad official)
- Symbol:
CBM6042AS8 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
cbm6042as8-etched.step/cbm6042as8-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cbm6042as8.step/cbm6042as8.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Corebai Microelectronics datasheet (17 pp, sha256
a233ac6d8521658f, retrieved 2026-10-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CBM6042AS8
**Corebai Microelectronics** · Operational Amplifier · SOP-8
CBM6042AS8 from Corebai Microelectronics, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTA | output | Amplifier A output, rail-to-rail swing. |
| 2 | INA- | input | Amplifier A inverting input; common-mode range VSS-0.1V to VDD+0.1V. |
| 3 | INA+ | input | Amplifier A non-inverting input; common-mode range VSS-0.1V to VDD+0.1V. |
| 4 | VSS | power_in | Negative supply or ground; for dual supply, bypass with a 0.1uF ceramic capacitor. |
| 5 | INB+ | input | Amplifier B non-inverting input; common-mode range VSS-0.1V to VDD+0.1V. |
| 6 | INB- | input | Amplifier B inverting input; common-mode range VSS-0.1V to VDD+0.1V. |
| 7 | OUTB | output | Amplifier B output, rail-to-rail swing. |
| 8 | VDD | power_in | Positive supply, 1.4V to 5.5V; place a 0.1uF ceramic capacitor close to the pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Corebai Microelectronics |
| Package | SOP-8 |
| Category | Amplifiers/Comparators |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Bias Current | IB | | 1 | | pA | | 3 |
| Input Offset Current | IOS | | 1 | | pA | | 3 |
| Common-Mode Voltage Range | VCM | -0.1 | | 5.6 | V | VS = 5.5V | 3 |
| Common-Mode Rejection Ratio | CMRR | 70 | 84 | | dB | VS = 5V, VCM = -0.1V to 2.5V | 3 |
| Common-Mode Rejection Ratio | CMRR | 67 | 83 | | dB | VS = 5V, VCM = -0.1V to 5.1V | 3 |
| Open-Loop Voltage Gain | AOL | 75 | 80 | | dB | VS=1.4V, RL = 50kΩ, VO = Vs-0.1V | 3 |
| Open-Loop Voltage Gain | AOL | 84 | 93 | | dB | VS=5V, RL = 50kΩ, VO = Vs-0.1V | 3 |
| Input Offset Voltage Drift | ΔVOS/ΔT | | 25 | | μV/℃ | | 3 |
| Output Voltage Swing from Rail (high) | VOH | 1.39 | 1.395 | | V | Vs=1.4V, RL = 50kΩ | 3 |
| Output Voltage Swing from Rail (low) | VOL | | 4.5 | 10 | mV | Vs=1.4V, RL = 50kΩ | 3 |
| Output Voltage Swing from Rail (high) | VOH | 4.99 | 4.997 | | V | Vs=5V, RL = 50kΩ | 3 |
| Output Voltage Swing from Rail (low) | VOL | | 3.5 | 10 | mV | Vs=5V, RL = 50kΩ | 3 |
| Output Current (source) | ISOURCE | 45 | 60 | 84 | mA | RL = 10Ω to VS/2 | 3 |
| Output Current (sink) | ISINK | 45 | 60 | 75 | mA | RL = 10Ω to VS/2 | 3 |
| Operating Voltage Range | VS | 1.4 | | 5.5 | V | | 3 |
| Power Supply Rejection Ratio | PSRR | 77 | 80 | | dB | VS=+1.4V to +5.5V, VCM=+0.5V | 3 |
| Quiescent Current / Amplifier | IQ | | 600 | | nA | | 3 |
| Gain-Bandwidth Product | GBP | | 15 | | KHz | CL = 100pF | 3 |
| Slew Rate | SR | | 4.5 | | V/ms | G = +1, 2V Output Step, CL = 100pF | 3 |
| Power Supply Voltage (VDD to VSS) | | -0.5 | | 7.5 | V | | 2 |
| Operating Temperature Range | | -40 | | 125 | ℃ | | 2 |
| Junction Temperature | | | | 160 | ℃ | | 2 |
| Storage Temperature Range | | -55 | | 150 | ℃ | | 2 |
| Lead Temperature | | | | 260 | ℃ | soldering, 10sec | 2 |
| Package Thermal Resistance SOP-8 | θJA | | 125 | | ℃/W | TA=+25℃ | 2 |
| ESD Susceptibility HBM | | | | 6 | KV | HBM | 2 |
| ESD Susceptibility MM | | | | 300 | V | MM | 2 |
## CAD (KiCad official)
- Symbol: `CBM6042AS8`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `cbm6042as8-etched.step` / `cbm6042as8-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cbm6042as8.step` / `cbm6042as8.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Corebai Microelectronics datasheet](docs/cbm6042as8-datasheet.pdf) (17 pp, sha256 `a233ac6d8521658f`, retrieved 2026-10-26, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cbm6042as8-datasheet.pdf)