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CBM53D24BMS

Public Made by Adom

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Corebai Microelectronics Digital To Analog Converters (DAC), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CBM53D24BMS

Corebai Microelectronics · Digital To Analog Converters (DAC) · MSOP-10

CBM53D24BMS from Corebai Microelectronics, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power supply input; these parts operate from 2.5V to 5.5V and the supply can be decoupled to GND.
2 VOUTA output Buffered analog output voltage from DAC A with rail-to-rail output amplifier operation.
3 VOUTB output Buffered analog output voltage from DAC B with rail-to-rail output amplifier operation.
4 VOUTC output Buffered analog output voltage from DAC C with rail-to-rail output amplifier operation.
5 Refin input Reference input pin for all four DACs with an input range from 0.25V to VDD.
6 VOUTD output Buffered analog output voltage from DAC D with rail-to-rail output amplifier operation.
7 GND power_in Ground reference point for all circuitry on the part.
8 Din input Serial data input to a 16-bit shift register, clocked in on the falling edge of Sclk; the Din buffer powers down after each write cycle.
9 Sclk input Serial clock input; data is clocked in on falling edges at clock speeds up to 30MHz, and the Sclk buffer powers down after each write cycle.
10 Sync input Active-low frame synchronization and chip-enable input; if taken high before the 16th falling Sclk edge, the write sequence is ignored.

Key specifications

Parameter Value
Manufacturer Corebai Microelectronics
Package MSOP-10
Category Data Acquisition
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD to GND VDDabs -0.3 7 V TA=25℃ 3
Digital Input Voltage to GND VDigabs -0.3 V TA=25℃ 3
Reference Input Voltage to GND Vrefabs -0.3 V TA=25℃ 3
VOUTA through VOUTD to GND Voutabs -0.3 V TA=25℃ 3
Operating Temperature Range (Industrial) -40 105 ℃ 3
Storage Temperature Range TS -65 150 ℃ 3
Junction Temperature TJmax 150 ℃ 3
Power supply VDD 2.5 5.5 V 3
Current dissipation IDD 400 600 uA 3
Ambient Temperature Ta -40 105 ℃ 3
Relative Accuracy INL (CBM53D24) INL -2 2 LSB 4
Differential Nonlinearity DNL (CBM53D24) DNL -0.2 0.2 LSB Monotonic guaranteed 4
Offset Error -0.4 0.4 %of FSR 4
Gain Error -0.15 0.15 %of FSR 4
VREF Input Range 0.25 V 4
Minimum Output Voltage 0 V 4
Input Low Voltage VIL 0.6 V VDD=3V 4
Input High Voltage VIH 2.1 V VDD=3V 5
SCLK cycle time (t1) t1 40 ns VDD=2.5V to 3.6V 6
SCLK cycle time (t1) t1 33 ns VDD=3.6V to 5.5V 6
SCLK high time (t2) t2 16 ns VDD=2.5V to 3.6V 6
SCLK high time (t2) t2 13 ns VDD=3.6V to 5.5V 6
SCLK low time (t3) t3 16 ns VDD=2.5V to 3.6V 6
SCLK low time (t3) t3 13 ns VDD=3.6V to 5.5V 6
SYNC to SCLK falling edge setup time (t4) t4 16 ns VDD=2.5V to 3.6V 6
SYNC to SCLK falling edge setup time (t4) t4 13 ns VDD=3.6V to 5.5V 6
Data setup time (t5) t5 5 ns VDD=2.5V to 3.6V 6
Data hold time (t6) t6 4.5 ns VDD=2.5V to 3.6V 6
SCLK falling edge to SYNC rising edge (t7) t7 0 ns VDD=2.5V to 3.6V 6
Minimum SYNC high time (t8) t8 80 ns VDD=2.5V to 3.6V 6
Minimum SYNC high time (t8) t8 33 ns VDD=3.6V to 5.5V 6
Lower Dead Band 20 mV Lower dead band exists only if offset error is negative 4
DC Power Supply Rejection Ratio PSRR -60 dB △VDD=±10% 4
DC Crosstalk 200 uV RL=2KΩ to GND or VDD 4
VREF Input Impedance 45 KΩ 4
Reference Feedthrough -80 dB Frequency=10KHz 4
Short Circuit Current 25 mA 4
Power-Up Time 5 uS 4
Pin Capacitance 3 pF 5
IDD (Normal Mode) IDD 600 uA VDD=4.5V to 5.5V 5
IDD (Normal Mode) IDD 500 uA VDD=2.5V to 3.6V 5
IDD (Power-Down Mode) IDD 0.2 uA VDD=4.5V to 5.5V; VIH=VDD and VIL=GND 5
IDD (Power-Down Mode) IDD 0.08 uA VDD=2.5V to 3.6V; VIH=VDD and VIL=GND 5
Output Voltage Settling Time (CBM53D24) 8 uS 1/4 scale to 3/4 scale change(0x100 to 0x300) 5
Slew Rate 0.7 V/uS 5
Major-Code Transition Glitch Energy 40 nV-sec 1 LSB change around major carry 5
Digital Feedthrough 1 nV-sec 6
Digital Crosstalk 1 nV-sec 6
DAC-to-DAC Crosstalk 3 nV-sec 6
Multiplying Bandwidth 200 kHz VREF=2V±0.1VP-P 6
Total Harmonic Distortion -70 dB VREF=2.5V±0.1VP-P; Frequency=10KHz 6

CAD (KiCad official)

  • Symbol: CBM53D24BMS
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: cbm53d24bms-etched.step / cbm53d24bms-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cbm53d24bms.step / cbm53d24bms.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Corebai Microelectronics datasheet (18 pp, sha256 664b142b3a67084b, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF