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CBM53D04BMS

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Corebai Microelectronics Digital To Analog Converters (DACs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CBM53D04BMS

Corebai Microelectronics · Digital To Analog Converters (DACs) · MSOP-10

CBM53D04BMS from Corebai Microelectronics, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power supply input operating from 2.5V to 5.5V, to be decoupled to GND.
2 VOUTA output Buffered analog output voltage from DAC A with rail-to-rail output amplifier.
3 VOUTB output Buffered analog output voltage from DAC B with rail-to-rail output amplifier.
4 VOUTC output Buffered analog output voltage from DAC C with rail-to-rail output amplifier.
5 Refin input Reference input pin for all four DACs with an input range from 0.25V to VDD.
6 VOUTD output Buffered analog output voltage from DAC D with rail-to-rail output amplifier.
7 GND power_in Ground reference point for all circuitry on the part.
8 Din input Serial data input to the 16-bit shift register, clocked in on the falling edge of Sclk; the input buffer powers down after each write cycle.
9 Sclk input Serial clock input, data clocked in on the falling edge at clock speeds up to 30MHz; the input buffer powers down after each write cycle.
10 Sync input Active-low frame synchronization input that enables the input shift register for 16 falling Sclk edges; taking it high before the 16th falling edge aborts the write.

Key specifications

Parameter Value
Manufacturer Corebai Microelectronics
Package MSOP-10
Category Data Converters
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply voltage VDD 2.5 5.5 V 3
Ambient temperature Ta -40 105 ℃ 3
VDD to GND VDDabs -0.3 7 V TA=25℃ 3
Operating temperature range -40 105 ℃ Industrial 3
Storage temperature range -65 150 ℃ 3
Junction temperature TJ max 150 ℃ 3
Peak reflow temperature (Pb-free) 260 ℃ 10 sec to 40 sec at peak 3
Relative accuracy INL -0.15 0.15 LSB CBM53D04 4
Differential nonlinearity DNL -0.02 0.02 LSB CBM53D04; Monotonic Guaranteed 4
Offset error -0.4 0.4 % of FSR 4
Gain error -0.15 0.15 % of FSR 4
Lower dead band 20 mV Lower dead band exists only if offset error is negative 4
DC power supply rejection ratio PSRR -60 dB △VDD=±10% 4
DC crosstalk 200 uV RL=2KΩ to GND or VDD 4
VREF input range VREF 0.25 5.5 V 0.25 to VDD 4
Input low voltage VIL 0.6 V VDD=3V 5
Input high voltage VIH 2.1 V VDD=3V 5
Power supply VDD 2.5 5.5 V 5
IDD normal mode IDD 600 uA VDD=4.5V to 5.5V VIH=VDD and VIL=GND 5
IDD normal mode IDD 500 uA VDD=2.5V to 3.6V VIH=VDD and VIL=GND 5
IDD power-down mode IDD 0.2 uA VDD=4.5V to 5.5V VIH=VDD and VIL=GND 5
IDD power-down mode IDD 0.08 uA VDD=2.5V to 3.6V VIH=VDD and VIL=GND 5
Output voltage setting time 7 uS CBM53D04 1/4 scale to 3/4 scale change(0x40 to 0xC0) 5
SCLK cycle time t1 40 ns VDD=2.5V to 3.6V 6
SCLK cycle time t1 33 ns VDD=3.6V to 5.5V 6
SCLK high time t2 16 ns VDD=2.5V to 3.6V 6
SCLK high time t2 13 ns VDD=3.6V to 5.5V 6
SCLK low time t3 16 ns VDD=2.5V to 3.6V 6
SCLK low time t3 13 ns VDD=3.6V to 5.5V 6
SYNC to SCLK falling edge setup time t4 16 ns VDD=2.5V to 3.6V 6
SYNC to SCLK falling edge setup time t4 13 ns VDD=3.6V to 5.5V 6
Data setup time t5 5 ns 6
Data hold time t6 4.5 ns 6
SCLK falling edge to SYNC rising edge t7 0 ns 6
Minimum SYNC high time t8 80 ns VDD=2.5V to 3.6V 6
Minimum SYNC high time t8 33 ns VDD=3.6V to 5.5V 6
Resolution ResN 8 Bits CBM53D04 4
VREF input impedance 45 KΩ 4
DC output impedance 0.5 Ω 4
Short circuit current 25 mA 5
Power-up time 5 uS 5
Slew rate 0.7 V/uS 6

CAD (KiCad official)

  • Symbol: CBM53D04BMS
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: cbm53d04bms-etched.step / cbm53d04bms-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cbm53d04bms.step / cbm53d04bms.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Corebai Microelectronics datasheet (18 pp, sha256 616aae75a6f97e6c, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF