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CBM53D04AMS
Public Made by Adomby adom
Corebai Microelectronics Digital To Analog Converters (DACs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCBM53D04AMS
Corebai Microelectronics · Digital To Analog Converters (DACs) · MSOP-10
CBM53D04AMS from Corebai Microelectronics, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Power supply input operating from 2.5V to 5.5V, to be decoupled to GND. |
| 2 | VOUTA | output | Buffered analog output voltage from DAC A with rail-to-rail output amplifier. |
| 3 | VOUTB | output | Buffered analog output voltage from DAC B with rail-to-rail output amplifier. |
| 4 | VOUTC | output | Buffered analog output voltage from DAC C with rail-to-rail output amplifier. |
| 5 | Refin | input | Reference input pin shared by all four DACs, with an input range from 0.25V to VDD. |
| 6 | VOUTD | output | Buffered analog output voltage from DAC D with rail-to-rail output amplifier. |
| 7 | GND | power_in | Ground reference point for all circuitry on the part. |
| 8 | Din | input | Serial data input to the 16-bit shift register, clocked in on the falling edge of Sclk; the input buffer powers down after each write cycle. |
| 9 | Sclk | input | Serial clock input, data clocked in on the falling edge at clock speeds up to 30MHz; the input buffer powers down after each write cycle. |
| 10 | Sync | input | Active-low frame synchronization input that enables the input shift register for 16 falling Sclk edges; taking it high before the 16th falling edge aborts the write. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Corebai Microelectronics |
| Package | MSOP-10 |
| Category | Data Converters |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD to GND | VDDabs | -0.3 | 7 | V | TA=25℃ | 3 | |
| Digital Input Voltage to GND | VDigabs | -0.3 | V | max is VDD+0.3V | 3 | ||
| Reference Input Voltage to GND | Vrefabs | -0.3 | V | max is VDD+0.3V | 3 | ||
| VOUTA through VOUTD to GND | Voutabs | -0.3 | V | max is VDD+0.3V | 3 | ||
| Operating Temperature Range (Industrial) | -40 | 105 | ℃ | Industrial | 3 | ||
| Storage Temperature Range | -65 | 150 | ℃ | 3 | |||
| Junction Temperature | TJ max | 150 | ℃ | 3 | |||
| Reflow Peak Temperature (Pb-free) | 260 | ℃ | Time at peak 10 sec to 40 sec | 3 | |||
| Power supply | VDD | 2.5 | 5.5 | V | 3 | ||
| Current dissipation | IDD | 400 | 600 | uA | printed as 400u / 600u A | 3 | |
| Ambient Temperature | Ta | -40 | 105 | ℃ | 3 | ||
| Relative Accuracy | INL | -0.15 | 0.15 | LSB | CBM53D04; VDD=2.5V to 5.5V; VREF=2V; RL=2KΩ; CL=200pF; Ta=25℃ | 4 | |
| Differential Nonlinearity | DNL | -0.02 | 0.02 | LSB | CBM53D04; Monotonic Guaranteed | 4 | |
| Offset Error | -0.4 | 0.4 | %of FSR | 4 | |||
| Gain Error | -0.15 | 0.15 | %of FSR | 4 | |||
| VREF Input Range | 0.25 | V | max printed as VDD | 4 | |||
| Power supply | VDD | 2.5 | 5.5 | V | 5 | ||
| IDD (Normal Mode) | IDD | 600 | uA | VDD=4.5V to 5.5V VIH=VDD and VIL=GND | 5 | ||
| IDD (Normal Mode) | IDD | 500 | uA | VDD=2.5V to 3.6V VIH=VDD and VIL=GND | 5 | ||
| IDD (Power-Down Mode) | IDD | 0.2 | uA | VDD=4.5V to 5.5V VIH=VDD and VIL=GND | 5 | ||
| IDD (Power-Down Mode) | IDD | 0.08 | uA | VDD=2.5V to 3.6V VIH=VDD and VIL=GND | 5 | ||
| SCLK cycle time | t1 | 40 | ns | VDD=2.5V to 3.6V | 6 | ||
| SCLK cycle time | t1 | 33 | ns | VDD=3.6V to 5.5V | 6 | ||
| SCLK high time | t2 | 16 | ns | VDD=2.5V to 3.6V | 6 | ||
| SCLK high time | t2 | 13 | ns | VDD=3.6V to 5.5V | 6 | ||
| SCLK low time | t3 | 16 | ns | VDD=2.5V to 3.6V | 6 | ||
| SCLK low time | t3 | 13 | ns | VDD=3.6V to 5.5V | 6 | ||
| SYNC to SCLK falling edge setup time | t4 | 16 | ns | VDD=2.5V to 3.6V | 6 | ||
| SYNC to SCLK falling edge setup time | t4 | 13 | ns | VDD=3.6V to 5.5V | 6 | ||
| Data setup time | t5 | 5 | ns | 6 | |||
| Data hold time | t6 | 4.5 | ns | 6 | |||
| SCLK falling edge to SYNC rising edge | t7 | 0 | ns | 6 | |||
| Minimum SYNC high time | t8 | 80 | ns | VDD=2.5V to 3.6V | 6 | ||
| Minimum SYNC high time | t8 | 33 | ns | VDD=3.6V to 5.5V | 6 | ||
| Resolution | ResN | 8 | Bits | CBM53D04 | 4 | ||
| Lower Dead Band | 20 | mV | exists only if offset error is negative | 4 | |||
| DC Power Supply Rejection Ratio | PSRR | -60 | dB | △VDD=±10% | 4 | ||
| VREF Input Impedance | 45 | KΩ | 4 | ||||
| DC Output Impedance | 0.5 | Ω | 4 | ||||
| Short Circuit Current | 25 | mA | 5 | ||||
| Power-Up Time | 5 | uS | 5 | ||||
| Output Voltage Setting Time | 7 | uS | CBM53D04; 1/4 scale to 3/4 scale change(0x40 to 0xC0) | 5 | |||
| Slew Rate | 0.7 | V/uS | 6 |
CAD (KiCad official)
- Symbol:
CBM53D04AMS - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
cbm53d04ams-etched.step/cbm53d04ams-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cbm53d04ams.step/cbm53d04ams.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Corebai Microelectronics datasheet (18 pp, sha256
616aae75a6f97e6c, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).