component

CBM27GS8

Public Made by Adom

by adom

Corebai Microelectronics Precision Op Amps, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentamplifiers-comparatorscbm27gs8factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7d ago
viewers cbm27gs8: viewers · Ray 7d ago
cbm27gs8-etched.glb Publish 0.1.0 · Ray 7d ago
cbm27gs8-etched.step cbm27gs8: factory component page (tier=lcsc) · Ray 7d ago
cbm27gs8-hero.glb cbm27gs8: hero GLB from the etched model (keeps the MPN mark) · Ray 7d ago
cbm27gs8-hero.overlay.json Publish 0.1.0 · Ray 7d ago
cbm27gs8.glb Publish 0.1.0 · Ray 7d ago
cbm27gs8.kicad_mod Publish 0.1.0 · Ray 7d ago
cbm27gs8.kicad_sym Publish 0.1.0 · Ray 7d ago
cbm27gs8.lbr Publish 0.1.0 · Ray 7d ago
cbm27gs8.step Publish 0.1.0 · Ray 7d ago
package.json Publish 0.1.0 · Ray 7d ago
page.json Set visibility: public · Ray 7d ago
README.md Publish 0.1.0 · Ray 7d ago

CBM27GS8

Corebai Microelectronics · Precision Op Amps · SOIC-8

CBM27GS8 from Corebai Microelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TRIM passive Input offset voltage trim pin, which gives an adjustment range of ±4.0 mV with a 10 kΩ potentiometer (Rp).
2 -IN input Inverting input of the op amp, with an input voltage range of ±11.0 V min at VS=±15 V.
3 +IN input Non-inverting input of the op amp, with an input voltage range of ±11.0 V min at VS=±15 V.
4 V- power_in Negative supply, where the total supply (V+ to V-) must be between 8 V (±4 V) and 44 V (±22 V) in the absolute maximum ratings.
5 NC unconnected No internal connection.
6 OUT output Op amp output, which swings ±10.0 V min into a 600 Ω load at VS=±15 V.
7 V+ power_in Positive supply, where the total supply (V+ to V-) must be between 8 V (±4 V) and 44 V (±22 V) in the absolute maximum ratings.
8 TRIM passive Input offset voltage trim pin, which gives an adjustment range of ±4.0 mV with a 10 kΩ potentiometer (Rp).

Key specifications

Parameter Value
Manufacturer Corebai Microelectronics
Package SOIC-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage VOS 30 100 μV 5
Input offset voltage drift TCVOS 0.4 1.9 μV/°C 5
Input offset current IOS 10 75 nA 5
Input offset voltage adjustment range -4 4 mV Rp=10kΩ 5
Input bias current IB 15 80 nA 5
Input voltage range IVR 11 12.2 V 5
Common-mode rejection ratio CMRR 110 125 dB VCM=±11.0V 5
Large-signal voltage gain AVO 700 1500 V/mV RL≥2KΩ,Vo=±10V 5
Large-signal voltage gain AVO 600 1500 V/mV RL≥600Ω,Vo=±11V 5
Output voltage range Vo 11 13.3 V RL ≥2KΩ 5
Output voltage range Vo 10 12 V RL ≥600Ω 5
Input noise voltage, peak-to-peak en p-p 0.1 0.25 μV p-p 0.1Hz~10Hz 5
Input noise voltage density en 3.8 8 nV/√Hz fo=10Hz 5
Input noise voltage density en 3.3 6 nV/√Hz fo=30Hz 5
Input noise voltage density en 3.1 5 nV/√Hz fo=1000Hz 5
Input noise current density in 1.8 4 pA/√Hz fo=10Hz 5
Input noise current density in 1.1 2.5 pA/√Hz fo=30Hz 5
Input noise current density in 0.5 0.7 pA/√Hz fo=1000Hz 5
Gain bandwidth product GBW 5 8 MHz 5
Output slew rate SR 1.7 2.8 V/us RL≥2KΩ 5
Power supply rejection ratio PSRR 95 120 dB VS=±4V~±18V 5
Power consumption Pd 105 175 mW 5
Supply voltage (V+ to V-) 8 44 V 3
Operating temperature -40 125 ℃ 3
Junction temperature 150 ℃ 3
Storage temperature -55 150 ℃ 3
Soldering temperature 300 ℃ 10 s soldering time 3
Thermal resistance, junction to case θJC 43 ℃/W SOP8, package outer surface 3
Thermal resistance, junction to ambient θJA 158 ℃/W SOP8, package printed circuit board 3

CAD (KiCad official)

  • Symbol: CBM27GS8
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: cbm27gs8-etched.step / cbm27gs8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cbm27gs8.step / cbm27gs8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Corebai Microelectronics datasheet (7 pp, sha256 bea45bf49c1b5b8f, retrieved 2026-10-20, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF