component

CAV25128VE-GT3

Public Made by Adom

by adom

onsemi EEPROM, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmemorycav25128ve-gt3factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cav25128ve-gt3: viewers · Ray
cav25128ve-gt3-etched.glb Publish 0.1.0 · Ray
cav25128ve-gt3-etched.step cav25128ve-gt3: factory component page (tier=mfr) · Ray
cav25128ve-gt3-hero.glb cav25128ve-gt3: hero GLB from the etched model (keeps the MPN mark) · Ray
cav25128ve-gt3-hero.overlay.json Publish 0.1.0 · Ray
cav25128ve-gt3.glb Publish 0.1.0 · Ray
cav25128ve-gt3.kicad_mod Publish 0.1.0 · Ray
cav25128ve-gt3.kicad_sym Publish 0.1.0 · Ray
cav25128ve-gt3.lbr Publish 0.1.0 · Ray
cav25128ve-gt3.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray

CAV25128VE-GT3

onsemi · EEPROM · SOIC-8

CAV25128VE-GT3 from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Active-low chip select input that enables the device; when high, SO is tri-stated and the device is in standby, and each session needs a high-to-low transition at start and low-to-high at end.
2 SO tri_state Serial data output that shifts data out on the falling edge of SCK in SPI modes (0,0) and (1,1) and is high impedance when CS is high or during hold.
3 WP input Write protect input; when held low with the WPEN bit set to 1, writing to the Status Register is disabled, and all writes are allowed when it is high.
4 VSS power_in Ground.
5 SI input Serial data input that accepts op-codes, addresses and data, latched on the rising edge of SCK in SPI modes (0,0) and (1,1).
6 SCK input Serial clock input from the host used to synchronize communication, with a maximum frequency of 10 MHz.
7 HOLD input Active-low hold input that pauses serial transmission when taken low with SCK low and resumes when taken high; tie to VCC when not used.
8 VCC power_in Power supply, 2.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature -45 130 °C 2
Storage Temperature -65 150 °C 2
Voltage on any Pin with Respect to Ground -0.5 6.5 V Note 1 2
Supply Voltage Range VCC 2.5 5.5 V 1
Ambient Temperature (Automotive Grade 1) TA -40 125 °C 2
Supply Current (Read Mode) ICCR 2 mA Read, SO open, fSCK = 10 MHz 2
Supply Current (Write Mode) ICCW 2 mA Write, CS = VCC 2
Standby Current ISB1 3 µA VIN = GND or VCC, CS = VCC, WP = VCC, VCC = 5.5 V 2
Standby Current ISB2 5 µA VIN = GND or VCC, CS = VCC, WP = GND, VCC = 5.5 V 2
Input Leakage Current IL -2 2 µA VIN = GND or VCC 2
Output Leakage Current ILO -2 2 µA CS = VCC, VOUT = GND or VCC 2
Output Low Voltage VOL 0.4 V IOL = 3.0 mA 2
Output Capacitance (SO) COUT 8 pF VOUT = 0 V, TA = 25°C, f = 1.0 MHz, VCC = +5.0 V 2
Input Capacitance (CS, SCK, SI, WP, HOLD) CIN 8 pF VIN = 0 V, TA = 25°C, f = 1.0 MHz, VCC = +5.0 V 2
Endurance NEND 1e+06 Program / Erase Cycles Page Mode, VCC = 5 V, 25°C 2
Data Retention TDR 100 Years 2
Clock Frequency fSCK 10 MHz DC to 10 MHz 3
Data Setup Time tSU 10 ns 3
Data Hold Time tH 10 ns 3
SCK High Time tWH 40 ns 3
SCK Low Time tWL 40 ns 3
HOLD to Output Low Z tLZ 25 ns 3
Input Rise Time tRI 2 µs Note 7 3
Input Fall Time tFI 2 µs Note 7 3
HOLD Setup Time tHD 0 ns 3
HOLD Hold Time tCD 10 ns 3
Output Valid from Clock Low tV 40 ns 3
Output Hold Time tHO 0 ns 3
Output Disable Time tDIS 20 ns 3
HOLD to Output High Z tHZ 25 ns 3
CS High Time tCS 40 ns 3
CS Setup Time tCSS 30 ns 3
CS Hold Time tCSH 30 ns 3
CS Inactive Setup Time tCNS 20 ns 3
CS Inactive Hold Time tCNH 20 ns 3
WP Setup Time tWPS 10 ns 3
WP Hold Time tWPH 10 ns 3
Write Cycle Time tWC 5 ms Note 8 3
Power-up to Read Operation tPUR 0.1 1 ms 3
Power-up to Write Operation tPUW 0.1 1 ms 3

CAD (KiCad official)

  • Symbol: CAV25128VE-GT3
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: cav25128ve-gt3-etched.step / cav25128ve-gt3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cav25128ve-gt3.step / cav25128ve-gt3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (13 pp, sha256 d52dca1979ea2cdb, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF