# CAV24C16YE-GT3

**onsemi** · EEPROM · TSSOP-8

CAV24C16YE-GT3 from onsemi, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connect on the CAV24C16, whose address inputs A0, A1 and A2 are not used because all three address bits are internal. |
| 2 | NC | unconnected | No connect on the CAV24C16, whose address inputs A0, A1 and A2 are not used because all three address bits are internal. |
| 3 | NC | unconnected | No connect on the CAV24C16, whose address inputs A0, A1 and A2 are not used because all three address bits are internal. |
| 4 | VSS | power_in | Ground. |
| 5 | SDA | bidirectional | Serial data I/O that receives input data and transmits EEPROM data, open drain in transmit mode, with data acquired on the positive SCL edge and delivered on the negative edge. |
| 6 | SCL | input | Serial clock input that accepts the clock generated by the I2C master. |
| 7 | WP | input | Write protect input that inhibits all write operations when pulled HIGH, and is pulled LOW internally when not driven. |
| 8 | VCC | power_in | Power supply, 2.5 V to 5.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-8 |
| Category | Memory |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Read Current | ICCR |  |  | 1 | mA | Read, fSCL = 400 kHz | 3 |
| Write Current | ICCW |  |  | 2 | mA | Write, fSCL = 400 kHz | 3 |
| Standby Current | ISB |  |  | 5 | µA | All I/O Pins at GND or VCC, TA = -40°C to +125°C | 3 |
| I/O Pin Leakage | IL |  |  | 2 | µA | Pin at GND or VCC | 3 |
| Input Low Voltage | VIL | -0.5 |  | 0.3 | V | max is 0.3 x VCC | 3 |
| Input High Voltage (A0, A1, A2, WP) | VIH | 0.7 |  | 0.5 | V | A0, A1, A2 and WP; min 0.7 x VCC, max VCC + 0.5 | 3 |
| Input High Voltage (SCL, SDA) | VIH | 0.7 |  | 5.5 | V | SCL and SDA; min 0.7 x VCC | 3 |
| Output Low Voltage | VOL |  |  | 0.4 | V | VCC > 2.5 V, IOL = 3 mA | 3 |
| SDA Pin Capacitance | CIN |  |  | 8 | pF | VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V | 3 |
| Other Pins Capacitance | CIN |  |  | 6 | pF | VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V | 3 |
| WP Input Current | IWP |  |  | 130 | µA | VIN < VIH, VCC = 5.5 V | 3 |
| WP Input Current | IWP |  |  | 120 | µA | VIN < VIH, VCC = 3.6 V | 3 |
| WP Input Current | IWP |  |  | 80 | µA | VIN < VIH, VCC = 2.5 V | 3 |
| WP Input Current | IWP |  |  | 2 | µA | VIN > VIH | 3 |
| Address Input Current (A0, A1, A2) | IA |  |  | 50 | µA | VIN < VIH, VCC = 5.5 V | 3 |
| Address Input Current (A0, A1, A2) | IA |  |  | 35 | µA | VIN < VIH, VCC = 3.6 V | 3 |
| Address Input Current (A0, A1, A2) | IA |  |  | 25 | µA | VIN < VIH, VCC = 2.5 V | 3 |
| Address Input Current (A0, A1, A2) | IA |  |  | 2 | µA | VIN > VIH | 3 |
| Clock Frequency (Fast) | FSCL |  |  | 400 | kHz | Fast | 4 |
| START Condition Hold Time (Fast) | tHD:STA | 0.6 |  |  | µs | Fast | 4 |
| Low Period of SCL Clock (Fast) | tLOW | 1.3 |  |  | µs | Fast | 4 |
| High Period of SCL Clock (Fast) | tHIGH | 0.6 |  |  | µs | Fast | 4 |
| START Condition Setup Time (Fast) | tSU:STA | 0.6 |  |  | µs | Fast | 4 |
| Data In Setup Time (Fast) | tSU:DAT | 100 |  |  | ns | Fast | 4 |
| SDA and SCL Rise Time (Fast) | tR |  |  | 300 | ns | Fast | 4 |
| SDA and SCL Fall Time (Fast) | tF |  |  | 300 | ns | Fast | 4 |
| STOP Condition Setup Time (Fast) | tSU:STO | 0.6 |  |  | µs | Fast | 4 |
| Bus Free Time Between STOP and START (Fast) | tBUF | 1.3 |  |  | µs | Fast | 4 |
| SCL Low to Data Out Valid (Fast) | tAA |  |  | 0.9 | µs | Fast | 4 |
| Data Out Hold Time (Fast) | tDH | 100 |  |  | ns | Fast | 4 |
| Noise Pulse Filtered at SCL and SDA Inputs | Ti |  |  | 100 | ns | Fast | 4 |
| WP Hold Time | tHD:WP | 2.5 |  |  | µs |  | 4 |
| Write Cycle Time | tWR |  |  | 5 | ms |  | 4 |
| Storage Temperature |  | -65 |  | 150 | °C |  | 2 |
| Voltage on any pin with respect to Ground |  | -0.5 |  | 6.5 | V | Note 1 | 2 |
| Supply Voltage Range | VCC | 2.5 |  | 5.5 | V |  | 1 |
| Operating Temperature | TA | -40 |  | 125 | °C |  | 3 |
| Endurance | NEND | 1e+06 |  |  | Program / Erase Cycles | Page Mode, VCC = 5 V, 25°C | 2 |
| Data Retention | TDR | 100 |  |  | Years |  | 2 |

## CAD (KiCad official)

- Symbol: `CAV24C16YE-GT3`
- Footprint: `Package_SO:TSSOP-8_3x3mm_P0.65mm`
- 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files: `cav24c16ye-gt3-etched.step` / `cav24c16ye-gt3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cav24c16ye-gt3.step` / `cav24c16ye-gt3.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/cav24c16ye-gt3-d.pdf) (13 pp, sha256 `88188724b7c008a4`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cav24c16ye-gt3-datasheet.pdf)