component
CAV24C16WE-GT3
Public Made by Adomby adom
onsemi EEPROM, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownCAV24C16WE-GT3
onsemi · EEPROM · SOIC-8
CAV24C16WE-GT3 from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connect; on the CAV24C16 the A0 address input is not used, so this pin has no internal function. |
| 2 | NC | unconnected | No connect; on the CAV24C16 the A1 address input is not used, so this pin has no internal function. |
| 3 | NC | unconnected | No connect; on the CAV24C16 the A2 address input is not used, so this pin has no internal function. |
| 4 | VSS | power_in | Ground. |
| 5 | SDA | bidirectional | Serial Data I/O pin that receives input data and transmits data stored in EEPROM; open drain in transmit mode, with VIH of 0.7 x VCC to 5.5 V. |
| 6 | SCL | input | Serial Clock input that accepts the serial clock generated by the Master, up to 400 kHz (Fast mode). |
| 7 | WP | input | Write Protect input that inhibits all write operations when pulled HIGH; pulled LOW internally when not driven. |
| 8 | VCC | power_in | Power supply, 2.5 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Endurance (Program/Erase Cycles) | NEND | 1e+06 | Program / Erase Cycles | Page Mode, VCC = 5 V, 25°C (Note 3) | 2 | ||
| Data Retention | TDR | 100 | Years | 2 | |||
| Storage Temperature | -65 | 150 | °C | 2 | |||
| Voltage on any pin with respect to Ground | -0.5 | 6.5 | V | Note 1 | 2 | ||
| Supply Voltage Range (VCC) | VCC | 2.5 | 5.5 | V | Stated in Features list | 1 | |
| Automotive Temperature Range | TA | -40 | 125 | °C | Stated in Features list (Automotive Temperature Grade 1) | 1 | |
| Read Current | ICCR | 1 | mA | Read, fSCL = 400 kHz | 3 | ||
| Write Current | ICCW | 2 | mA | Write, fSCL = 400 kHz | 3 | ||
| Standby Current | ISB | 5 | A | All I/O Pins at GND or VCC TA = −40°C to +125°C | 3 | ||
| I/O Pin Leakage | IL | 2 | A | Pin at GND or VCC | 3 | ||
| Input Low Voltage (lower limit) | VIL | -0.5 | V | 3 | |||
| Input Low Voltage (upper limit) | VIL | 0.3 | x VCC | 3 | |||
| Input High Voltage A0, A1, A2 and WP (lower limit) | VIH | 0.7 | x VCC | A0, A1, A2 and WP | 3 | ||
| Input High Voltage SCL and SDA (lower limit) | VIH | 0.7 | x VCC | SCL and SDA | 3 | ||
| Input High Voltage SCL and SDA (upper limit) | VIH | 5.5 | V | SCL and SDA | 3 | ||
| Output Low Voltage | VOL | 0.4 | V | VCC > 2.5 V, IOL = 3 mA | 3 | ||
| SDA Pin Capacitance | CIN | 8 | pF | VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V | 3 | ||
| Other Pins Capacitance | CIN | 6 | pF | 3 | |||
| WP Input Current | IWP | 130 | A | VIN < VIH, VCC = 5.5 V | 3 | ||
| WP Input Current | IWP | 120 | A | VIN < VIH, VCC = 3.6 V | 3 | ||
| WP Input Current | IWP | 80 | A | VIN < VIH, VCC = 2.5 V | 3 | ||
| WP Input Current | IWP | 2 | A | VIN > VIH | 3 | ||
| Address Input Current (A0, A1, A2) | IA | 50 | A | VIN < VIH, VCC = 5.5 V | 3 | ||
| Address Input Current (A0, A1, A2) | IA | 35 | A | VIN < VIH, VCC = 3.6 V | 3 | ||
| Address Input Current (A0, A1, A2) | IA | 25 | A | VIN < VIH, VCC = 2.5 V | 3 | ||
| Address Input Current (A0, A1, A2) | IA | 2 | A | VIN > VIH | 3 | ||
| Clock Frequency (Standard mode) | FSCL | 100 | kHz | 4 | |||
| Clock Frequency (Fast mode) | FSCL | 400 | kHz | 4 | |||
| START Condition Hold Time (Standard) | tHD:STA | 4 | s | 4 | |||
| START Condition Hold Time (Fast) | tHD:STA | 0.6 | s | 4 | |||
| Low Period of SCL Clock (Standard) | tLOW | 4.7 | s | 4 | |||
| Low Period of SCL Clock (Fast) | tLOW | 1.3 | s | 4 | |||
| High Period of SCL Clock (Standard) | tHIGH | 4 | s | 4 | |||
| High Period of SCL Clock (Fast) | tHIGH | 0.6 | s | 4 | |||
| START Condition Setup Time (Standard) | tSU:STA | 4.7 | s | 4 | |||
| START Condition Setup Time (Fast) | tSU:STA | 0.6 | s | 4 | |||
| Data In Hold Time (Standard) | tHD:DAT | 0 | s | 4 | |||
| Data In Hold Time (Fast) | tHD:DAT | 0 | s | 4 | |||
| Data In Setup Time (Standard) | tSU:DAT | 250 | ns | 4 | |||
| Data In Setup Time (Fast) | tSU:DAT | 100 | ns | 4 | |||
| SDA and SCL Rise Time (Standard) | tR | 1000 | ns | 4 | |||
| SDA and SCL Rise Time (Fast) | tR | 300 | ns | 4 | |||
| SDA and SCL Fall Time (Standard) | tF | 300 | ns | Note 6 | 4 | ||
| SDA and SCL Fall Time (Fast) | tF | 300 | ns | Note 6 | 4 | ||
| STOP Condition Setup Time (Standard) | tSU:STO | 4 | s | 4 | |||
| STOP Condition Setup Time (Fast) | tSU:STO | 0.6 | s | 4 | |||
| Bus Free Time Between STOP and START (Standard) | tBUF | 4.7 | s | 4 | |||
| Bus Free Time Between STOP and START (Fast) | tBUF | 1.3 | s | 4 | |||
| SCL Low to Data Out Valid (Standard) | tAA | 3.5 | s | 4 | |||
| SCL Low to Data Out Valid (Fast) | tAA | 0.9 | s | 4 | |||
| Data Out Hold Time (Standard) | tDH | 100 | ns | 4 | |||
| Data Out Hold Time (Fast) | tDH | 100 | ns | 4 | |||
| Noise Pulse Filtered at SCL and SDA Inputs (Standard) | Ti | 100 | ns | Note 6 | 4 | ||
| Noise Pulse Filtered at SCL and SDA Inputs (Fast) | Ti | 100 | ns | Note 6 | 4 | ||
| WP Setup Time (Standard) | tSU:WP | 0 | s | 4 | |||
| WP Setup Time (Fast) | tSU:WP | 0 | s | 4 | |||
| WP Hold Time (Standard) | tHD:WP | 2.5 | s | 4 | |||
| WP Hold Time (Fast) | tHD:WP | 2.5 | s | 4 | |||
| Write Cycle Time (Standard) | tWR | 5 | ms | 4 | |||
| Write Cycle Time (Fast) | tWR | 5 | ms | 4 | |||
| Power-up to Ready Mode (Standard) | tPU | 0.1 | ms | Notes 7, 8 | 4 | ||
| Power-up to Ready Mode (Fast) | tPU | 0.1 | ms | Notes 7, 8 | 4 |
CAD (KiCad official)
- Symbol:
CAV24C16WE-GT3 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
cav24c16we-gt3-etched.step/cav24c16we-gt3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cav24c16we-gt3.step/cav24c16we-gt3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (15 pp, sha256
5295a70c10e77f66, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).