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CAV24C08WE-GT3

Public Made by Adom

by adom

onsemi EEPROM, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CAV24C08WE-GT3

onsemi · EEPROM · SOIC-8

CAV24C08WE-GT3 from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connect on the CAV24C08; this pin is the A0 address input only on the CAV24C02.
2 NC unconnected No connect on the CAV24C08; this pin is the A1 address input only on the CAV24C04 and CAV24C02.
3 A2 input Device address input that sets the device address when cascading multiple devices (two CAV24C08 on one bus), pulled LOW internally when not driven.
4 VSS power_in Ground.
5 SDA bidirectional Serial data I/O pin that receives input data and transmits data stored in EEPROM, open drain in transmit mode.
6 SCL input Serial clock input that accepts the serial clock generated by the master, up to 400 kHz.
7 WP input Write protect input that inhibits all write operations when pulled HIGH, pulled LOW internally when not driven.
8 VCC power_in Power supply, 2.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Read Current ICCR 1 mA Read, fSCL = 400 kHz 3
Write Current ICCW 2 mA Write, fSCL = 400 kHz 3
Standby Current ISB 5 µA All I/O Pins at GND or VCC, TA = -40°C to +125°C 3
I/O Pin Leakage IL 2 µA Pin at GND or VCC 3
Input Low Voltage VIL -0.5 0.3 V max is 0.3 x VCC 3
Input High Voltage A0, A1, A2, WP VIH 0.7 0.5 V A0, A1, A2 and WP; min 0.7 x VCC, max VCC + 0.5 3
Input High Voltage SCL, SDA VIH 0.7 5.5 V SCL and SDA; min 0.7 x VCC 3
Output Low Voltage VOL 0.4 V VCC > 2.5 V, IOL = 3 mA 3
SDA Pin Capacitance CIN 8 pF VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V 3
Other Pins Capacitance CIN 6 pF VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V 3
WP Input Current IWP 130 µA VIN < VIH, VCC = 5.5 V 3
WP Input Current IWP 120 µA VIN < VIH, VCC = 3.6 V 3
WP Input Current IWP 80 µA VIN < VIH, VCC = 2.5 V 3
WP Input Current IWP 2 µA VIN > VIH 3
Address Input Current IA 50 µA VIN < VIH, VCC = 5.5 V 3
Address Input Current IA 35 µA VIN < VIH, VCC = 3.6 V 3
Address Input Current IA 25 µA VIN < VIH, VCC = 2.5 V 3
Address Input Current IA 2 µA VIN > VIH 3
Clock Frequency (Standard) FSCL 100 kHz Standard 4
Clock Frequency (Fast) FSCL 400 kHz Fast 4
START Hold Time (Standard) tHD:STA 4 µs Standard 4
START Hold Time (Fast) tHD:STA 0.6 µs Fast 4
SCL Low Period (Standard) tLOW 4.7 µs Standard 4
SCL Low Period (Fast) tLOW 1.3 µs Fast 4
SCL High Period (Standard) tHIGH 4 µs Standard 4
SCL High Period (Fast) tHIGH 0.6 µs Fast 4
START Setup Time (Standard) tSU:STA 4.7 µs Standard 4
START Setup Time (Fast) tSU:STA 0.6 µs Fast 4
Data In Hold Time tHD:DAT 0 µs Standard and Fast 4
Data In Setup Time (Standard) tSU:DAT 250 ns Standard 4
Data In Setup Time (Fast) tSU:DAT 100 ns Fast 4
SDA and SCL Rise Time (Standard) tR 1000 ns Standard 4
SDA and SCL Rise Time (Fast) tR 300 ns Fast 4
SDA and SCL Fall Time (Standard) tF 300 ns Standard 4
SDA and SCL Fall Time (Fast) tF 300 ns Fast 4
STOP Setup Time (Standard) tSU:STO 4 µs Standard 4
STOP Setup Time (Fast) tSU:STO 0.6 µs Fast 4
Bus Free Time (Standard) tBUF 4.7 µs Standard 4
Bus Free Time (Fast) tBUF 1.3 µs Fast 4
SCL Low to Data Out Valid (Standard) tAA 3.5 µs Standard 4
SCL Low to Data Out Valid (Fast) tAA 0.9 µs Fast 4
Data Out Hold Time tDH 100 ns Standard and Fast 4
Noise Pulse Filtered at SCL and SDA Ti 100 ns Standard and Fast 4
WP Setup Time tSU:WP 0 µs Standard and Fast 4
WP Hold Time tHD:WP 2.5 µs Standard and Fast 4
Write Cycle Time tWR 5 ms Standard and Fast 4
Power-up to Ready Mode tPU 0.1 ms Standard and Fast 4
Storage Temperature -65 150 °C 2
Voltage on any pin with respect to Ground -0.5 6.5 V Note 1 2
Endurance NEND 1e+06 Program / Erase Cycles Page Mode, VCC = 5 V, 25°C 2
Data Retention TDR 100 Years 2
Supply Voltage Range VCC 2.5 5.5 V 1
Operating Temperature TA -40 125 °C 3

CAD (KiCad official)

  • Symbol: CAV24C08WE-GT3
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: cav24c08we-gt3-etched.step / cav24c08we-gt3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cav24c08we-gt3.step / cav24c08we-gt3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (13 pp, sha256 88188724b7c008a4, retrieved 2026-10-24, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF