component
CAV24C02WE-GT3
Public Made by Adomby adom
onsemi EEPROM, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
CAV24C02WE-GT3
onsemi · EEPROM · SOIC-8
CAV24C02WE-GT3 from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Device address input (CAV24C02) that sets the device address when cascading multiple devices; pulled LOW internally when not driven. |
| 2 | A1 | input | Device address input that sets the device address when cascading multiple devices; pulled LOW internally when not driven. |
| 3 | A2 | input | Device address input that sets the device address when cascading multiple devices; pulled LOW internally when not driven. |
| 4 | VSS | power_in | Ground. |
| 5 | SDA | bidirectional | Serial data input/output, open drain in transmit mode; data is acquired on the positive edge and delivered on the negative edge of SCL. |
| 6 | SCL | input | Serial clock input that accepts the serial clock generated by the master. |
| 7 | WP | input | Write protect input that inhibits all write operations when pulled HIGH; pulled LOW internally when not driven. |
| 8 | VCC | power_in | Power supply, 2.5 V to 5.5 V supply voltage range. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Read Current | ICCR | 1 | mA | Read, fSCL = 400 kHz | 3 | ||
| Write Current | ICCW | 2 | mA | Write, fSCL = 400 kHz | 3 | ||
| Standby Current | ISB | 5 | A | All I/O Pins at GND or VCC, TA = −40°C to +125°C | 3 | ||
| I/O Pin Leakage | IL | 2 | A | Pin at GND or VCC | 3 | ||
| Input Low Voltage | VIL | -0.5 | V | 3 | |||
| Input Low Voltage (upper limit) | VIL | 0.3 | x VCC | 3 | |||
| Input High Voltage, A0, A1, A2 and WP (lower limit) | VIH | 0.7 | x VCC | A0, A1, A2 and WP | 3 | ||
| Input High Voltage, A0, A1, A2 and WP (upper limit, printed as VCC + 0.5 V) | VIH | 0.5 | V | A0, A1, A2 and WP; printed max is VCC + 0.5 V | 3 | ||
| Input High Voltage, SCL and SDA (lower limit) | VIH | 0.7 | x VCC | SCL and SDA | 3 | ||
| Input High Voltage, SCL and SDA (upper limit) | VIH | 5.5 | V | SCL and SDA | 3 | ||
| Output Low Voltage | VOL | 0.4 | V | VCC > 2.5 V, IOL = 3 mA | 3 | ||
| SDA Pin Capacitance | CIN | 8 | pF | VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V | 3 | ||
| Other Pins Capacitance | CIN | 6 | pF | 3 | |||
| WP Input Current | IWP | 130 | A | VIN < VIH, VCC = 5.5 V | 3 | ||
| WP Input Current | IWP | 120 | A | VIN < VIH, VCC = 3.6 V | 3 | ||
| WP Input Current | IWP | 80 | A | VIN < VIH, VCC = 2.5 V | 3 | ||
| WP Input Current | IWP | 2 | A | VIN > VIH | 3 | ||
| Address Input Current (A0, A1, A2) | IA | 50 | A | VIN < VIH, VCC = 5.5 V | 3 | ||
| Address Input Current (A0, A1, A2) | IA | 35 | A | VIN < VIH, VCC = 3.6 V | 3 | ||
| Address Input Current (A0, A1, A2) | IA | 25 | A | VIN < VIH, VCC = 2.5 V | 3 | ||
| Address Input Current (A0, A1, A2) | IA | 2 | A | VIN > VIH | 3 | ||
| Clock Frequency | FSCL | 100 | kHz | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| Clock Frequency | FSCL | 400 | kHz | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| START Condition Hold Time | tHD:STA | 4 | s | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| START Condition Hold Time | tHD:STA | 0.6 | s | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| Low Period of SCL Clock | tLOW | 4.7 | s | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| Low Period of SCL Clock | tLOW | 1.3 | s | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| High Period of SCL Clock | tHIGH | 4 | s | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| High Period of SCL Clock | tHIGH | 0.6 | s | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| START Condition Setup Time | tSU:STA | 4.7 | s | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| START Condition Setup Time | tSU:STA | 0.6 | s | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| Data In Hold Time | tHD:DAT | 0 | s | Standard and Fast modes; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| Data In Setup Time | tSU:DAT | 250 | ns | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| Data In Setup Time | tSU:DAT | 100 | ns | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| SDA and SCL Rise Time | tR | 1000 | ns | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| SDA and SCL Rise Time | tR | 300 | ns | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| SDA and SCL Fall Time (Note 6) | tF | 300 | ns | Standard and Fast modes; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| STOP Condition Setup Time | tSU:STO | 4 | s | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| STOP Condition Setup Time | tSU:STO | 0.6 | s | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| Bus Free Time Between STOP and START | tBUF | 4.7 | s | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| Bus Free Time Between STOP and START | tBUF | 1.3 | s | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| SCL Low to Data Out Valid | tAA | 3.5 | s | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| SCL Low to Data Out Valid | tAA | 0.9 | s | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| Data Out Hold Time | tDH | 100 | ns | Standard and Fast modes; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| Noise Pulse Filtered at SCL and SDA Inputs | Ti | 100 | ns | Standard and Fast modes; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| WP Setup Time | tSU:WP | 0 | s | Standard and Fast modes; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| WP Hold Time | tHD:WP | 2.5 | s | Standard and Fast modes; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| Write Cycle Time | tWR | 5 | ms | Standard and Fast modes; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| Power-up to Ready Mode | tPU | 0.1 | ms | Standard and Fast modes; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 | ||
| Input Rise and Fall Time | 50 | ns | AC test conditions | 4 | |||
| Endurance | NEND | 1e+06 | Program / Erase Cycles | Page mode, VCC = 5 V, 25°C | 2 | ||
| Data Retention | TDR | 100 | Years | 2 | |||
| Storage Temperature | -65 | 150 | °C | 2 | |||
| Voltage on any pin with respect to Ground | -0.5 | 6.5 | V | With respect to Ground (Note 1) | 2 | ||
| Supply Voltage | VCC | 2.5 | 5.5 | V | Operating range per Table 3 header | 3 | |
| Operating Temperature | TA | -40 | 125 | °C | Operating range per Table 3 header; Automotive Grade 1 | 3 |
CAD (KiCad official)
- Symbol:
CAV24C02WE-GT3 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
cav24c02we-gt3-etched.step/cav24c02we-gt3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cav24c02we-gt3.step/cav24c02we-gt3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (15 pp, sha256
5295a70c10e77f66, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CAV24C02WE-GT3
**onsemi** · EEPROM · SOIC-8
CAV24C02WE-GT3 from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Device address input (CAV24C02) that sets the device address when cascading multiple devices; pulled LOW internally when not driven. |
| 2 | A1 | input | Device address input that sets the device address when cascading multiple devices; pulled LOW internally when not driven. |
| 3 | A2 | input | Device address input that sets the device address when cascading multiple devices; pulled LOW internally when not driven. |
| 4 | VSS | power_in | Ground. |
| 5 | SDA | bidirectional | Serial data input/output, open drain in transmit mode; data is acquired on the positive edge and delivered on the negative edge of SCL. |
| 6 | SCL | input | Serial clock input that accepts the serial clock generated by the master. |
| 7 | WP | input | Write protect input that inhibits all write operations when pulled HIGH; pulled LOW internally when not driven. |
| 8 | VCC | power_in | Power supply, 2.5 V to 5.5 V supply voltage range. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Read Current | ICCR | | | 1 | mA | Read, fSCL = 400 kHz | 3 |
| Write Current | ICCW | | | 2 | mA | Write, fSCL = 400 kHz | 3 |
| Standby Current | ISB | | | 5 | A | All I/O Pins at GND or VCC, TA = −40°C to +125°C | 3 |
| I/O Pin Leakage | IL | | | 2 | A | Pin at GND or VCC | 3 |
| Input Low Voltage | VIL | -0.5 | | | V | | 3 |
| Input Low Voltage (upper limit) | VIL | | | 0.3 | x VCC | | 3 |
| Input High Voltage, A0, A1, A2 and WP (lower limit) | VIH | 0.7 | | | x VCC | A0, A1, A2 and WP | 3 |
| Input High Voltage, A0, A1, A2 and WP (upper limit, printed as VCC + 0.5 V) | VIH | | | 0.5 | V | A0, A1, A2 and WP; printed max is VCC + 0.5 V | 3 |
| Input High Voltage, SCL and SDA (lower limit) | VIH | 0.7 | | | x VCC | SCL and SDA | 3 |
| Input High Voltage, SCL and SDA (upper limit) | VIH | | | 5.5 | V | SCL and SDA | 3 |
| Output Low Voltage | VOL | | | 0.4 | V | VCC > 2.5 V, IOL = 3 mA | 3 |
| SDA Pin Capacitance | CIN | | | 8 | pF | VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V | 3 |
| Other Pins Capacitance | CIN | | | 6 | pF | | 3 |
| WP Input Current | IWP | | | 130 | A | VIN < VIH, VCC = 5.5 V | 3 |
| WP Input Current | IWP | | | 120 | A | VIN < VIH, VCC = 3.6 V | 3 |
| WP Input Current | IWP | | | 80 | A | VIN < VIH, VCC = 2.5 V | 3 |
| WP Input Current | IWP | | | 2 | A | VIN > VIH | 3 |
| Address Input Current (A0, A1, A2) | IA | | | 50 | A | VIN < VIH, VCC = 5.5 V | 3 |
| Address Input Current (A0, A1, A2) | IA | | | 35 | A | VIN < VIH, VCC = 3.6 V | 3 |
| Address Input Current (A0, A1, A2) | IA | | | 25 | A | VIN < VIH, VCC = 2.5 V | 3 |
| Address Input Current (A0, A1, A2) | IA | | | 2 | A | VIN > VIH | 3 |
| Clock Frequency | FSCL | | | 100 | kHz | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| Clock Frequency | FSCL | | | 400 | kHz | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| START Condition Hold Time | tHD:STA | 4 | | | s | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| START Condition Hold Time | tHD:STA | 0.6 | | | s | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| Low Period of SCL Clock | tLOW | 4.7 | | | s | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| Low Period of SCL Clock | tLOW | 1.3 | | | s | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| High Period of SCL Clock | tHIGH | 4 | | | s | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| High Period of SCL Clock | tHIGH | 0.6 | | | s | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| START Condition Setup Time | tSU:STA | 4.7 | | | s | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| START Condition Setup Time | tSU:STA | 0.6 | | | s | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| Data In Hold Time | tHD:DAT | 0 | | | s | Standard and Fast modes; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| Data In Setup Time | tSU:DAT | 250 | | | ns | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| Data In Setup Time | tSU:DAT | 100 | | | ns | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| SDA and SCL Rise Time | tR | | | 1000 | ns | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| SDA and SCL Rise Time | tR | | | 300 | ns | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| SDA and SCL Fall Time (Note 6) | tF | | | 300 | ns | Standard and Fast modes; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| STOP Condition Setup Time | tSU:STO | 4 | | | s | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| STOP Condition Setup Time | tSU:STO | 0.6 | | | s | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| Bus Free Time Between STOP and START | tBUF | 4.7 | | | s | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| Bus Free Time Between STOP and START | tBUF | 1.3 | | | s | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| SCL Low to Data Out Valid | tAA | | | 3.5 | s | Standard mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| SCL Low to Data Out Valid | tAA | | | 0.9 | s | Fast mode; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| Data Out Hold Time | tDH | 100 | | | ns | Standard and Fast modes; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| Noise Pulse Filtered at SCL and SDA Inputs | Ti | | | 100 | ns | Standard and Fast modes; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| WP Setup Time | tSU:WP | 0 | | | s | Standard and Fast modes; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| WP Hold Time | tHD:WP | 2.5 | | | s | Standard and Fast modes; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| Write Cycle Time | tWR | | | 5 | ms | Standard and Fast modes; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| Power-up to Ready Mode | tPU | | | 0.1 | ms | Standard and Fast modes; VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C | 4 |
| Input Rise and Fall Time | | | | 50 | ns | AC test conditions | 4 |
| Endurance | NEND | 1e+06 | | | Program / Erase Cycles | Page mode, VCC = 5 V, 25°C | 2 |
| Data Retention | TDR | 100 | | | Years | | 2 |
| Storage Temperature | | -65 | | 150 | °C | | 2 |
| Voltage on any pin with respect to Ground | | -0.5 | | 6.5 | V | With respect to Ground (Note 1) | 2 |
| Supply Voltage | VCC | 2.5 | | 5.5 | V | Operating range per Table 3 header | 3 |
| Operating Temperature | TA | -40 | | 125 | °C | Operating range per Table 3 header; Automotive Grade 1 | 3 |
## CAD (KiCad official)
- Symbol: `CAV24C02WE-GT3`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `cav24c02we-gt3-etched.step` / `cav24c02we-gt3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cav24c02we-gt3.step` / `cav24c02we-gt3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588879936358920192) (15 pp, sha256 `5295a70c10e77f66`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cav24c02we-gt3-datasheet.pdf)