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CAT34C02YI-GT5A

onsemi · EEPROM · TSSOP-8

CAT34C02YI-GT5A from onsemi, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Device address input with an on-chip pull-down; selects one of 8 possible slave devices and accepts the very high voltage VHV (7 V to 10 V) for RSWP operations.
2 A1 input Device address input with an on-chip pull-down; selects one of 8 possible slave devices.
3 A2 input Device address input with an on-chip pull-down; selects one of 8 possible slave devices.
4 VSS power_in Ground.
5 SDA bidirectional Serial data input/output that receives input data and transmits EEPROM data, open drain in transmit mode.
6 SCL input Serial clock input that accepts the clock generated by the master.
7 WP input Write protect input with an on-chip pull-down that inhibits all write operations when pulled HIGH.
8 VCC power_in Power supply, 1.7 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature -45 130 °C 2
Storage Temperature -65 150 °C 2
Voltage on Any Pin with Respect to Ground -0.5 6.5 V 2
Voltage on Pin A0 with Respect to Ground -0.5 10.5 V 2
Supply Current ICC 1 mA VCC < 3.6 V, fSCL = 100 kHz 2
Supply Current ICC 2 mA VCC > 3.6 V, fSCL = 400 kHz 2
Standby Current ISB 1 µA All I/O pins at GND or VCC; TA = −40°C to +85°C; VCC ≤ 3.3 V 2
Standby Current ISB 3 µA All I/O pins at GND or VCC; TA = −40°C to +85°C; VCC > 3.3 V 2
I/O Pin Leakage IL 2 µA Pin at GND or VCC 2
Input Low Voltage VIL -0.5 V 2
Input High Voltage VIH 4 V SDA and SCL, VCC = 0 V (footnote *) 2
Output Low Voltage VOL 0.4 V VCC > 2.5 V, IOL = 3 mA 2
Output Low Voltage VOL 0.2 V VCC < 2.5 V, IOL = 1 mA 2
SDA I/O Pin Capacitance CIN 8 pF VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V 2
Other Input Pins Capacitance CIN 6 pF 2
WP Input Current IWP 130 µA VIN < VIH, VCC = 5.5 V 2
WP Input Current IWP 120 µA VIN < VIH, VCC = 3.6 V 2
WP Input Current IWP 80 µA VIN < VIH, VCC = 1.7 V 2
Address Input Current (A0, A1, A2) IA 50 µA VIN < VIH, VCC = 5.5 V 2
Address Input Current (A0, A1, A2) IA 35 µA VIN < VIH, VCC = 3.6 V 2
Address Input Current (A0, A1, A2) IA 25 µA VIN < VIH, VCC = 1.7 V 2
Clock Frequency FSCL 100 kHz Standard mode 3
Clock Frequency FSCL 400 kHz Fast mode 3
START Condition Hold Time tHD:STA 4 µs Standard mode 3
START Condition Hold Time tHD:STA 0.6 µs Fast mode 3
Low Period of SCL Clock tLOW 4.7 µs Standard mode 3
Low Period of SCL Clock tLOW 1.3 µs Fast mode 3
High Period of SCL Clock tHIGH 4 µs Standard mode 3
High Period of SCL Clock tHIGH 0.6 µs Fast mode 3
START Condition Setup Time tSU:STA 4.7 µs Standard mode 3
START Condition Setup Time tSU:STA 0.6 µs Fast mode 3
Data Hold Time tHD:DAT 0 µs Standard mode 3
Data Setup Time tSU:DAT 250 ns Standard mode 3
Data Setup Time tSU:DAT 100 ns Fast mode 3
SDA and SCL Rise Time tR 1000 ns Standard mode 3
SDA and SCL Rise Time tR 300 ns Fast mode 3
SDA and SCL Fall Time tF 300 ns Standard mode 3
STOP Condition Setup Time tSU:STO 4 µs Standard mode 3
STOP Condition Setup Time tSU:STO 0.6 µs Fast mode 3
Bus Free Time Between STOP and START tBUF 4.7 µs Standard mode 3
Bus Free Time Between STOP and START tBUF 1.3 µs Fast mode 3
SCL Low to SDA Data Out tAA 3.5 µs Standard mode 3
SCL Low to SDA Data Out tAA 0.9 µs Fast mode 3
Data Out Hold Time tDH 100 ns Standard mode 3
Noise Pulse Filtered at SCL and SDA Inputs Ti 100 ns Standard mode 3
WP Setup Time tSU:WP 0 µs Standard mode 3
WP Hold Time tHD:WP 2.5 µs Standard mode 3
Write Cycle Time tWR 5 ms 3
Power-up to Ready Mode tPU 1 ms 3
A0 Overdrive (VHV − VCC) VHV 4.8 V 1.7 V < VCC < 3.6 V 8
A0 Very High Voltage VHV 7 10 V 8
A0 Input Current @ VHV IHV 1 mA 8
Junction-to-Ambient Thermal Resistance (TSSOP) JA 64 °C/W Air velocity = 0 m/s, 4 layers PCB 3
Junction-to-Case Thermal Resistance (TSSOP) JC 37 °C/W Air velocity = 0 m/s, 4 layers PCB 3

CAD (KiCad official)

  • Symbol: CAT34C02YI-GT5A
  • Footprint: Package_SO:TSSOP-8_4.4x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: cat34c02yi-gt5a-etched.step / cat34c02yi-gt5a-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cat34c02yi-gt5a.step / cat34c02yi-gt5a.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (14 pp, sha256 7ffdef766c3b2de8, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF