component

CAT24M01YI-GT3

Public Made by Adom

by adom

onsemi EEPROM, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmemorycat24m01yi-gt3factory-2.0.0extractor-text

Verified CAT24M01YI-GT3

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CAT24M01YI-GT3 · TSSOP-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 14-page datasheet
  • ✓distributor: lcsc C233776, digikey CAT24M01YI-GT3OSTR-ND, mouser 863-CAT24M01YI-GT3
  • ✓family: TSSOP-8_3x3mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-4qm8xfff/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare (datasheet p.13)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cat24m01yi-gt3.kicad_sym✓ cat24m01yi-gt3.kicad_mod✓ cat24m01yi-gt3.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
cat24m01yi-gt3 / README.md
History Download
Ray Publish 0.1.0 6ce3d59

CAT24M01YI-GT3

onsemi · EEPROM · TSSOP-8

CAT24M01YI-GT3 from onsemi, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connect pin; the datasheet gives no function for it.
2 A1 input Device address input that selects one of up to four devices on the bus, with an on-chip pull-down resistor.
3 A2 input Device address input that selects one of up to four devices on the bus, with an on-chip pull-down resistor.
4 VSS power_in Ground.
5 SDA bidirectional Serial data I/O that receives input data and transmits stored data, open drain when transmitting.
6 SCL input Serial clock input that accepts the clock signal generated by the master.
7 WP input Write protect input that inhibits all write operations when pulled HIGH, with an on-chip pull-down resistor.
8 VCC power_in Power supply, 1.8 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature -65 150 °C 2
Voltage on any Pin with Respect to Ground -0.5 6.5 V Note 1 2
Supply Voltage Range VCC 1.8 5.5 V 1
Operating Temperature Range (Industrial) TA -40 85 °C 9
Read Current ICCR 1 mA Read, fSCL = 400 kHz / 1 MHz 2
Write Current ICCW 3.5 mA VCC = 1.8 V 2
Write Current ICCW 5 mA VCC = 5.5 V 2
Standby Current ISB 2 µA All I/O Pins at GND or VCC; TA = −40°C to +85°C 2
I/O Pin Leakage IL 1 µA Pin at GND or VCC; TA = −40°C to +85°C 2
Input Low Voltage VIL1 -0.5 V 2.5 V ≤ VCC ≤ 5.5 V 2
Output Low Voltage VOL1 0.4 V VCC ≥ 2.5 V, IOL = 3.0 mA 2
Output Low Voltage VOL2 0.2 V VCC < 2.5 V, IOL = 1.0 mA 2
SDA I/O Pin Capacitance CIN 8 pF VIN = 0 V 3
Input Capacitance (other pins) CIN 6 pF VIN = 0 V 3
WP Input Current, Address Input Current (A1, A2) IWP, IA 75 µA VIN < VIH, VCC = 5.5 V 3
WP Input Current, Address Input Current (A1, A2) IWP, IA 50 µA VIN < VIH, VCC = 3.3 V 3
WP Input Current, Address Input Current (A1, A2) IWP, IA 25 µA VIN < VIH, VCC = 1.8 V 3
WP Input Current, Address Input Current (A1, A2) IWP, IA 2 µA VIN > VIH 3
FSCL Clock Frequency FSCL 100 kHz Standard, VCC = 1.8 V − 5.5 V 3
FSCL Clock Frequency FSCL 400 kHz Fast, VCC = 1.8 V − 5.5 V 3
FSCL Clock Frequency FSCL 1000 kHz Fast-Plus, VCC = 2.5 V − 5.5 V 3
START Condition Hold Time tHD:STA 4 µs Standard, VCC = 1.8 V − 5.5 V 3
START Condition Hold Time tHD:STA 0.6 µs Fast, VCC = 1.8 V − 5.5 V 3
START Condition Hold Time tHD:STA 0.25 µs Fast-Plus, VCC = 2.5 V − 5.5 V 3
Low Period of SCL Clock tLOW 4.7 µs Standard, VCC = 1.8 V − 5.5 V 3
Low Period of SCL Clock tLOW 1.3 µs Fast, VCC = 1.8 V − 5.5 V 3
Low Period of SCL Clock tLOW 0.45 µs Fast-Plus, VCC = 2.5 V − 5.5 V 3
High Period of SCL Clock tHIGH 4 µs Standard, VCC = 1.8 V − 5.5 V 3
High Period of SCL Clock tHIGH 0.6 µs Fast, VCC = 1.8 V − 5.5 V 3
High Period of SCL Clock tHIGH 0.4 µs Fast-Plus, VCC = 2.5 V − 5.5 V 3
START Condition Setup Time tSU:STA 4.7 µs Standard, VCC = 1.8 V − 5.5 V 3
START Condition Setup Time tSU:STA 0.6 µs Fast, VCC = 1.8 V − 5.5 V 3
START Condition Setup Time tSU:STA 0.25 µs Fast-Plus, VCC = 2.5 V − 5.5 V 3
Data In Setup Time tSU:DAT 250 ns Standard, VCC = 1.8 V − 5.5 V 3
Data In Setup Time tSU:DAT 100 ns Fast, VCC = 1.8 V − 5.5 V 3
Data In Setup Time tSU:DAT 50 ns Fast-Plus, VCC = 2.5 V − 5.5 V 3
SDA and SCL Rise Time tR 1000 ns Standard, VCC = 1.8 V − 5.5 V 3
SDA and SCL Rise Time tR 300 ns Fast, VCC = 1.8 V − 5.5 V 3
SDA and SCL Rise Time tR 100 ns Fast-Plus, VCC = 2.5 V − 5.5 V 3
SDA and SCL Fall Time tF 300 ns Standard, VCC = 1.8 V − 5.5 V 3
SDA and SCL Fall Time tF 100 ns Fast-Plus, VCC = 2.5 V − 5.5 V 3
STOP Condition Setup Time tSU:STO 4 µs Standard, VCC = 1.8 V − 5.5 V 3
STOP Condition Setup Time tSU:STO 0.6 µs Fast, VCC = 1.8 V − 5.5 V 3
STOP Condition Setup Time tSU:STO 0.25 µs Fast-Plus, VCC = 2.5 V − 5.5 V 3
Bus Free Time Between STOP and START tBUF 4.7 µs Standard, VCC = 1.8 V − 5.5 V 3
Bus Free Time Between STOP and START tBUF 1.3 µs Fast, VCC = 1.8 V − 5.5 V 3
Bus Free Time Between STOP and START tBUF 0.5 µs Fast-Plus, VCC = 2.5 V − 5.5 V 3
SCL Low to Data Out Valid tAA 3.5 µs Standard, VCC = 1.8 V − 5.5 V 3
SCL Low to Data Out Valid tAA 0.9 µs Fast, VCC = 1.8 V − 5.5 V 3
SCL Low to Data Out Valid tAA 0.4 µs Fast-Plus, VCC = 2.5 V − 5.5 V 3
Data Out Hold Time tDH 50 ns Standard, VCC = 1.8 V − 5.5 V 3
Write Cycle Time tWR 5 ms Standard, VCC = 1.8 V − 5.5 V 3

CAD (KiCad official)

  • Symbol: CAT24M01YI-GT3
  • Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: cat24m01yi-gt3-etched.step / cat24m01yi-gt3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cat24m01yi-gt3.step / cat24m01yi-gt3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (14 pp, sha256 12aee0725ccfa61d, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF