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CAT24C512YI-GT3

Public Made by Adom

by adom

onsemi EEPROM, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CAT24C512YI-GT3

onsemi · EEPROM · TSSOP-8

CAT24C512YI-GT3 from onsemi, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Device address input bit 0, selects one of 8 devices on the bus, with an on-chip pull-down resistor.
2 A1 input Device address input bit 1, selects one of 8 devices on the bus, with an on-chip pull-down resistor.
3 A2 input Device address input bit 2, selects one of 8 devices on the bus, with an on-chip pull-down resistor.
4 VSS power_in Ground.
5 SDA bidirectional Serial data I/O pin that receives input data and transmits stored data, open drain in transmit mode.
6 SCL input Serial clock input accepting the clock signal generated by the master, supporting up to 1 MHz.
7 WP input Write protect input that inhibits all write operations when pulled HIGH, with an on-chip pull-down resistor.
8 VCC power_in Power supply, 1.8 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC 1.8 5.5 V TA = -40°C to +85°C 3
Operating temperature TA -40 85 °C CAT24C512YI-GT3 17
Storage Temperature -65 150 °C 3
Voltage on any Pin with Respect to Ground -0.5 6.5 V Note 1 3
Read Current ICCR 1 mA Read, fSCL = 400 kHz/1 MHz 3
Write Current ICCW 1.8 mA VCC = 1.8 V 3
Write Current ICCW 2.5 mA VCC = 5.5 V 3
Standby Current ISB 2 µA All I/O Pins at GND or VCC, TA = -40°C to +85°C 3
I/O Pin Leakage IL 1 µA Pin at GND or VCC, TA = -40°C to +85°C 3
Output Low Voltage VOL1 0.4 V VCC ≥ 2.5 V, IOL = 3.0 mA 3
Output Low Voltage VOL2 0.2 V VCC < 2.5 V, IOL = 1.0 mA 3
SDA I/O Pin Capacitance CIN 8 pF VIN = 0 V 3
Input Capacitance (other pins) CIN 6 pF VIN = 0 V 3
WP/Address Input Current IWP, IA 75 µA VIN < VIH, VCC = 5.5 V 3
WP/Address Input Current IWP, IA 50 µA VIN < VIH, VCC = 3.3 V 3
WP/Address Input Current IWP, IA 25 µA VIN < VIH, VCC = 1.8 V 3
WP/Address Input Current IWP, IA 2 µA VIN > VIH 3
Endurance NEND 1e+06 Program/Erase Cycles Page Mode, VCC = 5 V, 25°C 3
Data Retention TDR 100 Years 3
Clock Frequency FSCL 100 kHz Standard, VCC = 1.8 V − 5.5 V 4
Clock Frequency FSCL 400 kHz Fast, VCC = 1.8 V − 5.5 V 4
Clock Frequency FSCL 1000 kHz Fast-Plus, VCC = 2.5 V − 5.5 V 4
Write Cycle Time tWR 5 ms 4
START Condition Hold Time tHD:STA 0.6 µs Fast, VCC = 1.8 V − 5.5 V 4
Low Period of SCL Clock tLOW 1.3 µs Fast, VCC = 1.8 V − 5.5 V 4
High Period of SCL Clock tHIGH 0.6 µs Fast, VCC = 1.8 V − 5.5 V 4
START Condition Setup Time tSU:STA 0.6 µs Fast, VCC = 1.8 V − 5.5 V 4
Data In Hold Time tHD:DAT 0 µs Fast, VCC = 1.8 V − 5.5 V 4
Data In Setup Time tSU:DAT 100 ns Fast, VCC = 1.8 V − 5.5 V 4
SDA and SCL Rise Time tR 300 ns Fast, VCC = 1.8 V − 5.5 V 4
SDA and SCL Fall Time tF 300 ns Fast, VCC = 1.8 V − 5.5 V 4
STOP Condition Setup Time tSU:STO 0.6 µs Fast, VCC = 1.8 V − 5.5 V 4
Bus Free Time Between STOP and START tBUF 1.3 µs Fast, VCC = 1.8 V − 5.5 V 4
SCL Low to Data Out Valid tAA 0.9 µs Fast, VCC = 1.8 V − 5.5 V 4
Data Out Hold Time tDH 50 ns Fast, VCC = 1.8 V − 5.5 V 4
Noise Pulse Filtered at SCL and SDA Inputs Ti 50 ns Fast, VCC = 1.8 V − 5.5 V 4
WP Setup Time tSU:WP 0 µs Fast, VCC = 1.8 V − 5.5 V 4
WP Hold Time tHD:WP 2.5 µs Fast, VCC = 1.8 V − 5.5 V 4
START Condition Hold Time tHD:STA 0.25 µs Fast-Plus, VCC = 2.5 V − 5.5 V 4
Low Period of SCL Clock tLOW 0.45 µs Fast-Plus, VCC = 2.5 V − 5.5 V 4
High Period of SCL Clock tHIGH 0.4 µs Fast-Plus, VCC = 2.5 V − 5.5 V 4
START Condition Setup Time tSU:STA 0.25 µs Fast-Plus, VCC = 2.5 V − 5.5 V 4
Data In Setup Time tSU:DAT 50 ns Fast-Plus, VCC = 2.5 V − 5.5 V 4
SDA and SCL Rise Time tR 100 ns Fast-Plus, VCC = 2.5 V − 5.5 V 4
SDA and SCL Fall Time tF 100 ns Fast-Plus, VCC = 2.5 V − 5.5 V 4
STOP Condition Setup Time tSU:STO 0.25 µs Fast-Plus, VCC = 2.5 V − 5.5 V 4
Bus Free Time Between STOP and START tBUF 0.5 µs Fast-Plus, VCC = 2.5 V − 5.5 V 4
SCL Low to Data Out Valid tAA 0.4 µs Fast-Plus, VCC = 2.5 V − 5.5 V 4
WP Hold Time tHD:WP 1 µs Fast-Plus, VCC = 2.5 V − 5.5 V 4

CAD (KiCad official)

  • Symbol: CAT24C512YI-GT3
  • Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: cat24c512yi-gt3-etched.step / cat24c512yi-gt3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cat24c512yi-gt3.step / cat24c512yi-gt3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (17 pp, sha256 174dee97153cad86, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF