# CAP005DG-TL

**POWER INTEGRATIONS** · Power Management Specialized - PMIC · SO-8

CAP005DG-TL from POWER INTEGRATIONS, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | Not electrically connected; the datasheet recommends coupling pins 1-4 and pins 5-8 together on the PCB. |
| 2 | D1 | passive | One of the two high-voltage terminals of the CAPZero, connected to the X capacitor through external resistor R1 and R2; the DRAIN pin voltage (D1 relative to D2, either polarity) must not exceed 825 V for CAP005. |
| 3 | D1 | passive | Second pin of terminal D1, to be coupled to pin 2 on the PCB; the DRAIN pin voltage (D1 relative to D2, either polarity) must not exceed 825 V for CAP005. |
| 4 | NC | unconnected | Not electrically connected; the datasheet recommends coupling pins 1-4 and pins 5-8 together on the PCB. |
| 5 | NC | unconnected | Not electrically connected; the datasheet recommends coupling pins 1-4 and pins 5-8 together on the PCB. |
| 6 | D2 | passive | One of the two high-voltage terminals of the CAPZero, connected to the X capacitor through external resistor R1 and R2; the DRAIN pin voltage (D1 relative to D2, either polarity) must not exceed 825 V for CAP005. |
| 7 | D2 | passive | Second pin of terminal D2, to be coupled to pin 6 on the PCB; the DRAIN pin voltage (D1 relative to D2, either polarity) must not exceed 825 V for CAP005. |
| 8 | NC | unconnected | Not electrically connected; the datasheet recommends coupling pins 1-4 and pins 5-8 together on the PCB. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | POWER INTEGRATIONS |
| Package | SO-8 |
| Category | Power Supply Chip |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DRAIN Peak Current |  |  |  | 1.667 | mA | CAP005/015; allowed while DRAIN voltage is simultaneously less than 400 V | 4 |
| Storage Temperature |  | -65 |  | 150 | °C |  | 4 |
| Operating Ambient Temperature |  | -10 |  | 105 | °C |  | 4 |
| Maximum Junction Temperature |  | -10 |  | 110 | °C |  | 4 |
| AC Removal Detection Time | tDETECT | 22 | 31.4 |  | ms | Line cycle frequency 47-63 Hz | 4 |
| Drain Saturation Current | IDSAT | 0.78 |  |  | mA | CAP005/015; see Note A (natural RC discharge at all voltages up to 265 VAC pk) | 4 |
| Supply Current | ISUPPLY |  |  | 21.7 | mA | TA = 25 °C | 4 |
| Thermal Resistance Junction-to-Case (Top), D package | θJC |  | 75 |  | °C/W | Top | 4 |
| Maximum Total X Capacitance |  |  |  | 1.5 | mF | CAP005DG (825 V) per Component Selection Table 1 | 1 |
| Total Series Resistance (R1 + R2) | R1 + R2 |  | 480 |  | kΩ | Nominal external resistance for CAP005DG per Component Selection Table 1 | 1 |

## CAD (KiCad official)

- Symbol: `CAP005DG-TL`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `cap005dg-tl-etched.step` / `cap005dg-tl-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cap005dg-tl.step` / `cap005dg-tl.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [POWER INTEGRATIONS datasheet](docs/cap005dg-tl-datasheet.pdf) (8 pp, sha256 `f7b939d2d28e6d48`, retrieved 2026-10-30, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cap005dg-tl-datasheet.pdf)